I heard we're posting FPGA builds

[c0ff33]

I've completed my initial version of Michael Schröder's proposed design for Hack using Olimex ICE40HX1K-EVB, MOD-LCD2-8RTP & Olimexino-32u4.  I plan to make a modified version with PS/2 + VGA support using the iCE40-IO expansion board next but I ended up spending a few weeks updating and polishing the docs including entirely new content + test bench for the NS2009 RTP chip which came out in a later hardware revision than what they were originally using.

Some misc photos of the build during development: https://imgur.com/a/Prd5EIw

Retrospective

Compared to some of the later designs I have seen you can definitely buy more capable boards that abstract away a lot of these implementation details (at a higher cost though probably not that much higher if buying all of the above). The implementation effort required for Hack itself is relatively low compared to writing controllers for all the different ICs/serial interfaces and bringing it all together into a coherent system so your mileage may vary depending on how deeply you want to get into FPGA dev and some of the electrical engineering aspects. For me it was my first time doing any form of hardware dev so some areas required a bit more learning than others on my part.

I made some changes to restore API compatibility with the original nand2tetris API for Jack OS but largely due to the inclusion of the LCD and touch screen it is not really possible to run most existing Jack code relying on Screen/Keyboard I/O without some changes, that is something I hope to tackle more fully in the next version but expanding the spec to a colour screen & touch interface was still interesting to see/implement.

Show me the code!

Source: https://github.com/c0ff33-dev/nand2tetris-fpga

[c0ff33]

Once again taking inspiration from Michael Schröder, I decided I wanted to build something more faithful to the original nand2tetris spec which means adding VGA and PS/2 support via iCE40-IO and dropping MOD-LCD2.8RTP.

This ended up being not too bad to add the controllers (using his implementation for those, thanks Michael) but it required a really complex series of architectural updates to essentially pipeline all the different accesses to SRAM which unfortunately does not support dual port access. Without any way to parallelize those accesses I had to drop the clock speed as well from 25 MHz to 6.25 MHz just so there was enough time in each "cycle" (which is now several sub-phases but for the sake of nand2tetris semantics some things had to be maintained) for all the RAM accesses to complete (fetch instruction, read VRAM, read/write SRAM).

After these updates I was more or less able to plug in all my original Jack libraries with minimal changes, currently only needs to remap some of the previous memory mapped I/O devices and full ABI & API compatibility will be restored.

I'm happy with the result but a lot of this pain could have simply been abstracted away with a more capable board and perhaps I was being a bit stubborn there.

https://github.com/c0ff33-dev/nand2tetris-fpga/tree/main/09_More_Fun_to_Go