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I'm working on my last chip in chapter/week 3: the PC chip
I thought I had the implementation solved but am getting an error. I decided to compare my output with the compare file, and noticed something that didn't look right:
https://www.screencast.com/t/oK0UiI3KCw
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Administrator
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Your reset=0, load=1, and inc=1.
What does the chip specification say should happen under those conditions?
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In order to understand tick-tock, I used the builtin PC chip and went through Figure 3.5 of book step-by-step; I also watched "Unit 3.4 Counters" a couple of times. I think I understand the clock/cycle now.
Thanks.
My implementation is still failing, however. I'll create a schematic and send over later today.
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This post was updated on .
I'm having issues with my inc implementation. I've tried putting Inc16 in front and behind Register.
Interestingly, both scenarios (placing Inc16 before and after Register) failed at tick (1+ and 3+). I wouldn't think that the failure would happen at tock when the output happens and not when components are "loaded".
Appreciate a gentle nudge :)
https://www.dropbox.com/s/a98x9kbo7sy1o2j/PC-implementation.png?dl=0Regarding the question you ask upon my original post:
WBahn wrote
Your reset=0, load=1, and inc=1.
What does the chip specification say should happen under those conditions?
I would say the answer would be: load in at tick and output in at tock.
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Administrator
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You're making it much harder than it is.
Your PC only needs to store a single 16-bit value. That's it. One 16-bit value. So you need just one 16-bit register. Nothing more (in the way of storage).
You have to store one of four possible 16-bit values into that register on each clock cycle. So you need a way to select from among four possible 16-bit values. What device do you have that lets you do that? Let's call that device Bob. How many control input signals does it have?
The four possible values are zero, the value on the 'in' port, the value on the 'out' port, and the value on the 'out' port plus one. Can you get those four values to the data input ports of Bob?
Now you just have to come up with some logic to take your three control signals and generate the control signals for Bob.
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Administrator
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Congratulations.
You don't need a Mux8Way16. Since there are only 4 possible signals, a Mux4Way16 will work. You do need to add just a bit of decode logic to turn your three control signals into two control signals.
Either way works.
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This post was updated on .
Would I need more than 1 additional component?
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Administrator
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Probably. But they would be small components, whereas a Mux8Way16 is a pretty big component.
You were basically there with the truth table you had posted previously.
You had all eight possibilities of (reset, load, inc) listed along with the corresponding action (reset, load, increment, hold) -- you called the 'hold' action 'else'.
Now you just have to add two columns, one for each of the Mux4Way16 control bits. You now have two truth tables (one for each control bit). Design the logic for each one separately.
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Administrator
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You have the right idea.
Keep in mind that you have some options in that you control which signals go to which input, and by making different assignments (there are 24 possibilities) you get different logic, so some will be "better" than others.
I don't think the one you've chosen is all the bad -- it may or may not be the "best".
Consider your sel[1] signal. You have six terms with three signals in each term. If you look at it closely, you can do it with a single two-input logic gate. Your sel[0] signal also reduces down quite a bit, but not as much.
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This post was updated on .
Are you saying that my 6-term canonical expression for sel[1] can be reduced to a single two-input logic gate?
I know there are algebraic rules to assist in reducing canonical expressions. Can you please share how you would tackle this job.
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Administrator
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ouverson wrote
Are you saying that my 6-term canonical expression for sel[1] can be reduced to a single two-input logic gate?
I know there are algebraic rules to assist in reducing canonical expressions. Can you please share how you would tackle this job.
There are several ways to do it. In this case, just looking at the truth table reveals the logic -- but it takes a bit of experience to spot it. Since I've told you that it can be done with a single two-input OR gate, go through and consider all three possibilities. After you find the one that works, look at the truth table and see if you can spot the pattern that makes it fairly evident that that's the logic that is needed.
A more formal way of doing it is using Karnaugh maps, which are a visual technique for minimizing logic equations (where "minimal" is constrained by being in one of two standard forms).
And, yes, you can do it directly from your logic equation; but this is a bit cumbersome and relies on some level of skill and practice in Boolean algebra, which is both simpler and harder than normal algebra.
Consider part of your sel[1] expression:
R'LI' + R'LI
This can be written as
R'L(I' + I)
But anything OR'ed with its complement is always True (or 1), so this becomes
R'L(1)
Now, anything AND'ed with 1 is just itself, leaving us with
R'LI' + R'LI = R'L
See if you can work it from there. Get as far as you can and post what you've got and we'll push through whatever roadblock you come up against.
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When you say, "... three possibilities" what are you referencing? The only thing that stands out to me is the order of reset, load, and inc columns; if that's the case, how would that change the canonical expression? There would still be 6 terms with exactly the same values per term (just rearranged values.)
I keep hearing about Karnaugh maps; I suppose I should investigate.
In the meantime, I'll work on reducing my sel[1] expression, with the goal of getting to the 2 input OR gate.
Really appreciate your time. Thanks.
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Administrator
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ouverson wrote
When you say, "... three possibilities" what are you referencing? The only thing that stands out to me is the order of reset, load, and inc columns; if that's the case, how would that change the canonical expression? There would still be 6 terms with exactly the same values per term (just rearranged values.)
I keep hearing about Karnaugh maps; I suppose I should investigate.
In the meantime, I'll work on reducing my sel[1] expression, with the goal of getting to the 2 input OR gate.
Really appreciate your time. Thanks.
The three possibilities refers to the three ways to combined three signals using a single two-input OR gate.
If I have signals A, B, and C. Then the only options I have under that constraint are:
A Or B
A Or C
B Or C
Notice that this means that, whatever I do, there is one signal that I am ignoring completely. That means that, given the values of the two that I'm not ignoring, that I know the value that output needs to be regardless of what the value of the third happens to be. Do you see that behavior in your truth table?
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This post was updated on .
Answer to sel[1] input: OR gate with reset and load as inputs.
Answer to sel[0] input: 2 NOT gates, 2 AND gates, and 1 OR gate.
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Administrator
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In general it's preferred that you not edit posts in such a way that it completely changes the content -- forums are archival by nature and so edits should be confined to fixing typos or clarifying content. It's better to just make a new post. Also, editing a post does not result in people being notified of the change, so people following the thread will have no idea that there is new stuff -- I just happen to notice that there seemed to be something new as I was checking something else.
Your solution for sel[0] will work, but it can be simplified further. What would happen if you eliminated the requirement that reset be 0 in order to cover the one case that is not covered by reset = 1? It would result in two rows being a 1, the one that you are trying to cover (001) and one that is already covered (101). But there's no harm in covering rows multiple ways so the fact that (101) also happens to be covered by the other signal going into the Or gate doesn't matter. That one change will eliminate a Not gate and an And gate.
To improve on this requires taking the internals of the gates into account -- something that the Nand-2-Tetris projects makes difficult because of the focus on building everything from Nand gates.
To give you some idea of the difference this can make, in CMOS your current solution would use 22 transistors and the delay from input to output is seven times the time it takes to go through a single NAND gate (a unit of time called a "gate delay"). If we just make the change I talked about above, that reduces it to 14 transistors and five gate delays. If we take the internals into account, we can get it down to 12 transistors and only three gate delays. Using a direct CMOS implementation (instead of building it up using discrete logic gates) we can get it down to 10 transistors and just two gate delays.
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This post was updated on .
I'll make sure to follow your advice regarding editing my posts.
Following your hints, I will attempt to reduce the complexity of sel[0] even further.
Thank you for taking the time to explain the hardware performance issues, and considerations. I think the physical implementation is interesting and is the reason I wanted to simplify my PC implementation.
Aside: It would be nice if there was another course that took the hardware into consideration; with the availability and affordability of hardware components (Arduino, Raspberry Pi, etc.) I think this would be possible. It might involve a small investment in tools and components, but $300 or $400 goes a long way these days.
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Administrator
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Platforms like Arduino and Raspberry Pi aren't really appropriate for this project because they already have this stuff built into them -- they are essentially CPUs just like the Hack is a CPU.
A number of people have built the Hack (or other simplified processors) using discrete logic components, but the widespread value and utility of doing so is pretty limited.
But doing what you suggest would be a good paper project for an IC design course. Also, moving the Hack into physical hardware and dealing with the physical implementation of real memory-mapped peripherals is a very educational undertaking.
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This post was updated on .
I had to look at this for a while and read and reread your "What would happen if ..." until I could "see" the answer.
sel[0] ---> 1 NOT, 1 AND and 1 OR
When reset==1 then sel[0]=1, when reset==0 then sel[0]=0 other than when load==0 and inc==1; in that one case, reset==1 "covers".
This is curious work; I'm always trying to find the method, the procedure to accomplish a task; more often than not what helps me solve the problem at hand is "living with" the parts and pieces for a bit; letting it absorb; waiting for the pattern to appear. Reminds me of those pictures that were popular a decade or so back: the ones you'd stare at for a few minutes until the brain could "see" the image within the image.
Take this implementation of the sel[0] input; I'm not sure I would have "seen it" unless you would have nudged here and hinted there: from my Mux8Way, to my larger canonical expressions, to the sel[1] being a simple OR gate (I should have seen that one!) to this last one which (in my humble opinion) wasn't that obvious.
Thanks so much for your help.
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