Implementation of Nand2Tetris in Verilog

[giuseros85]

Hi all,
First of all, let me say that this course was amazing, one of the best I had!

I followed it last year, mostly because I was interested in the hardware part, since I wanted to learn concepts about hw development, hardware description languages, etc...

So, after I followed few other Verilog on-line courses I was able to implement the project on the DE10-Lite board in Verilog! I built a CPU!

This is the project home:
https://github.com/giuseros/nand2tetris

It's working, but for some reasons it's still a bit slow. Any suggestions, hints, directions, etc.. Are highly appreciated!

Thanks,
Giuseppe

[ivant]

Very impressive!

I wish I could help you with the slowness, but I have zero experience with Verilog or FPGA in general. There are a few other posts for similar projects in the forum. I'm not sure if any of them include the source code, but it might pay off reading through them.

One of the peculiarities of HACK's architecture is the very low limit of CPU registers: just A, D and PC. This means that almost every other executed instruction is memory access. Perhaps you can optimize this in your implementation.