Implementing a zero/negate chip

[acasimpsonz]

Maybe I took the book's advice too literally when I created a chip that simply zeroed and then negated a 16-bit input based on "z" and "n" in order to help with the ALU.  However, I am coming up with an error message "unexpected end of file" when I try to load it.  ZeroNegate.hdl

Can anyone tell me if there is a problem with the syntax or if I am even allowed to create a new chip like this without other structural changes?

[cadet1620]

acasimpsonz wrote

Maybe I took the book's advice too literally when I created a chip that simply zeroed and then negated a 16-bit input based on "z" and "n" in order to help with the ALU.  However, I am coming up with an error message "unexpected end of file" when I try to load it.

Can anyone tell me if there is a problem with the syntax or if I am even allowed to create a new chip like this without other structural changes?

I did the same thing when I implemented the ALU, creating a chip to handle the zero/negate.  Read carefully, by the way -- should you be doing a numerical negation or a logical negation -- the language tripped me up the first time through.

As for the unexpected end of file, whenever a compiler tells me this I look for mismatched (), {}, etc.

Mux16 is a really cool part by the way.  I figured out how to use them to get the zero/negate down to just a couple of lines of HDL so I moved it back into my ALU and did away with the sub-chip.

Read the section about buses in Appendix A.  Very useful, especially how true and false work with them.

--Mark

[acasimpsonz]

Wow thanks for the help. You answered questions I didn't even know that I had.  Now I have three lines of code too!

[cadet1620]

acasimpsonz wrote

Now I have three lines of code too!

I just thought of another "optimization" for the input processors and got mine down to two lines of HDL, still using only chips from the project 1 inventory.  Think about doing the entire operation in parallel instead of serially.  It's just a cute trick, though.  The source may be 33% shorter, but unfortunately the gate count is nearly 50% higher!

(Gate count is how many NAND gates it would take to implement a chip.  For instance, in this environment NAND and NOT have GC=1, AND would have GC=2 since it's made from two chips, etc.  GC for my ALU, not including this change, is 1125 compared with 466 for the one I implemented with only NAND gates.  http://questions-and-answers-forum.32033.n3.nabble.com/Why-we-like-abstraction-tp1914023p1914023.html)

Cheers!
--Mark