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Hi, I have been going at the program counter for a few hours now and I think I have a solution which I think should work but it's failing the tests with a difference of 1.
This is my HDL code
CHIP PC {
IN in[16], reset, load, inc;
OUT out[16];
PARTS:
//// Replace this comment with your code.
Register(in=resetloadincOutput, load=doiLoad, out=registerOut);
Or(a=load , b=inc, out=loadSometime);
Or(a=loadSometime, b=reset, out=doiLoad);
Inc16(in=out2 , out=outInc);
Mux16(a=registerOut , b=in, sel=load , out=out2 );
Mux16(a=out2 , b=outInc , sel=inc , out=outIncLoad );
Mux16(a=outIncLoad, b=false, sel=reset, out=resetloadincOutput);
Mux16(a=registerOut , b=registerOut , sel=reset , out=out);
}
I have taken some help of AI, mostly asking Yes / No questions (posted below).
"For the program counter, here’s all the help I gave you:
1. Said no when you asked whether (reset, load, inc, false) could go into the sel input of DMux4Way.
2. Confirmed that incrementing requires storing the incremented value in the register, so the register must load
when inc is asserted.
3. Said you don’t need more than one register or incrementer.
4. Explained that the PC’s external load input and its internal Register’s load pin don’t have to be the same
signal—the internal pin can be driven by logic.
5. Confirmed that resetting also requires storing the reset value.
6. Confirmed your three-way OR idea and explicitly gave load OR inc OR reset.
7. After seeing your HDL, said it was close, but flagged control priority and when the output changes as
remaining issues."
I would really appreciate if someone could tell me if these kind of questions are fine because I wanna learn / think the most I can for myself without relying too much on help.
I also did see the the implementation section of the book which said it can be done with Muxes.
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Administrator
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This post was updated on .
reinzmet wrote
Hi, I have been going at the program counter for a few hours now and I think I have a solution which I think should work but it's failing the tests with a difference of 1.
Failing every test with a difference of 1, or is it passing most of them and then finally failing one test with a difference of 1?
This is my HDL code
CHIP PC {
IN in[16], reset, load, inc;
OUT out[16];
PARTS:
//// Replace this comment with your code.
Register(in=resetloadincOutput, load=doiLoad, out=registerOut);
Or(a=load , b=inc, out=loadSometime);
Or(a=loadSometime, b=reset, out=doiLoad);
Inc16(in=out2 , out=outInc);
Mux16(a=registerOut , b=in, sel=load , out=out2 );
Mux16(a=out2 , b=outInc , sel=inc , out=outIncLoad );
Mux16(a=outIncLoad, b=false, sel=reset, out=resetloadincOutput);
Mux16(a=registerOut , b=registerOut , sel=reset , out=out);
}
Take a look at that last Mux16. What purpose is it serving? Whether reset is 0 or 1, the output is the same.
If you are using it because you don't know how to get the output of the Register to go both to the final chip output and go to other parts, that is addressed in the HDL Survival Guide. You can do it like the following example:
Nand(a=oneSignal, b=anotherSignal, out=internalSignal, out=out);
I have taken some help of AI, mostly asking Yes / No questions (posted below).
"For the program counter, here’s all the help I gave you:
1. Said no when you asked whether (reset, load, inc, false) could go into the sel input of DMux4Way.
2. Confirmed that incrementing requires storing the incremented value in the register, so the register must load
when inc is asserted.
3. Said you don’t need more than one register or incrementer.
4. Explained that the PC’s external load input and its internal Register’s load pin don’t have to be the same
signal—the internal pin can be driven by logic.
5. Confirmed that resetting also requires storing the reset value.
6. Confirmed your three-way OR idea and explicitly gave load OR inc OR reset.
7. After seeing your HDL, said it was close, but flagged control priority and when the output changes as
remaining issues."
I would really appreciate if someone could tell me if these kind of questions are fine because I wanna learn / think the most I can for myself without relying too much on help.
It's certainly better than just asking it to tell you how to do it. I would recommend making a concerted effort to solve it without using AI at all, but at least your approach has you doing most of the thinking.
I also did see the the implementation section of the book which said it can be done with Muxes.
The tests look at situations in which multiple control inputs are asserted at the same time. What happens in your code if both 'load' and 'inc' are asserted?
Yes, you can do it with Muxes a couple of different ways. You can do it with cascaded 2:1 Muxes, which is what you are trying to do, or you can do it with a single 8:1 Mux.
Let's assume that the Register currently has the value 1234 stored in it. Make a list of what value should be stored in the Register for every possible combination of load, inc, and reset. That's your Rosetta Stone.
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This post was updated on .
Much thanks, I got it!
CHIP PC {
IN in[16], reset, load, inc;
OUT out[16];
PARTS:
//// Replace this comment with your code.
<CODE SNIPPED>
I don't think this is the most optimal solution though.
I'm using 3 or gates to decide if i want to load or not.
And then again using a NAND gate and an AND gate to decide if i want to select the output of the LOAD bit vs the output of the INC bit
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Administrator
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You're correct that it's not the tightest solution. But, for these projects, functionality matters by far the most.
The PC can be implemented using just five parts. Think of the if-else description of its functionality and how the behavior of a Mux can be described in those same terms.
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I did get away with the OR gates by asserting the load to always be true for the register. I thought about trying to use the MUX gates for getting the same functionality as NAND and AND but didn't make much progress. Maybe I will do this when revisiting all chapters.
Thanks for your help!
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Locked
