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Hi, I am new to this forum. So I am on Project 5 and am working on the Memory.hdl implementation. The thing is I wrote the HDL and I cannot find a fault with it. However the test always fails at Line 53. Now when I Googled it , I found a few other implementations on Github that were very similar to mine and it turned out they also failed the test. So after some digging around I found their test files are different and quite a bit shorter.
Is this a well known bug or something across the community? Did the tests just get updated in the past 2-3 years to cover more edge cases? Or did they just write their own test cases?
Here is my implementation for reference:
CHIP Memory {
IN in[16], load, address[15];
OUT out[16];
PARTS:
// Put your code here:
DMux(in=load, sel=address[14], a=loadmemory, b=loadperi); // Check if normal RAM or peripherals
DMux(in=loadperi, sel=address[13], a=loadscreen, b=loadkeeb); //Screen or Keyboard
RAM16K(in=in, load=loadmemory, address=address[0..13], out=outram);
Screen(in=in, load=loadscreen, address=address[0..12], out=outscreen);
Keyboard(out=outkeeb);
Mux16(a=outscreen, b=outkeeb, sel=address[13], out=out1);
Mux16(a=outram, b=out1, sel=address[14], out=out);
}
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