The Nand2Tetris course is really amazing.
I wanted something to help me go from using the simplified HDL used in the course to learning to use Verilog.
Therefore, I made a python tool to convert HDL code to Verilog. The tool will also generate Verilog testbench files from the tst files, so the converted code can be tested against the cmp files used by the Hardware Simulator.
I used it to convert and test my answers for exercises 1 to 3.
https://github.com/tariqbashir-uk/nand2tetris-hdl2verilogHopefully the tool maybe useful to other people.
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