Missed scenario in PC's tests

[Tomer Even]

Hello,
I tried implementing the PC chip in several ways, and finally I passed the comparison test.
I was surprised to find out that I passed it although I did not deal with a specific situation,
and therefor I got wrong output for it:

| time | in  | reset | load  | inc | out  |
|  t0   |  0  |   0     |   1    |  0  |  ?    |
|  t0+ |  0  |   0    |   1    |  0   |  0   |
|  t1   |  X  |   0    |   0    |  0   |  0   |
|  t1+ |  X  |   0    |   0    |  0   |  X   |
|  t2   |  Y  |   0    |   0     |  0  |  X   |
|  t2+ |  Y  |   0    |   0    |  0   |  Y   |
|  t3   |  Z  |   0    |   0    |  0   |  Y   |
|  t3+ |  Z  |   0    |   0    |  0   |  Z   |

Which is obviously right only when x=y=z=0.

The build-in chip does not behave this way, therefor I thought this scenario was missed.
Is that correct? or did I do something wrong?

[cadet1620]

| time | in  | reset | load | inc | out |
|  t0+ |  0  |   0   |   1  |  0  |  ?  | 
|  t1  |  X  |   0   |   0  |  0  |  0  |
|  t1+ |  X  |   0   |   0  |  0  |  X  |
|  t2  |  Y  |   0   |   0  |  0  |  X  |
|  t2+ |  Y  |   0   |   0  |  0  |  Y  |
|  t3  |  Z  |   0   |   0  |  0  |  Y  |
|  t3+ |  Z  |   0   |   0  |  0  |  Z  |

When load = 0, in is ignored. out will be set to 0 at t1, and will remain 0 for the remainder of this sequence.

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--Mark