Mux16, works in Vizualiser but not in Simulator

[hdllearn]

Hi All,

I cannot find why the Hardware simulator is not accepting input a[1], ...a[15]. It says out of Bus range

However the Mux16.hdl works perfectly in the vizualiser.

Is this a bug in the Simulator? Or some other reasos?

There is no error for a[0].

Please help.

Thanks .

[WBahn]

Need to see your code in order to figure out what is going on.

Please post it -- we can delete it later, if appropriate.

[hdllearn]

  Not(in=sel, out=notSel);


   Mux(a=a[0], b[0]=sel, sel=sel, out=muxab);
   Mux(a=a[0], b[0]=notSel, sel=sel, out=muxcd);
   Or(a[1]=muxab, b[1]=muxcd, out=out[0]);



  Mux(a=a[1], b[1]=sel, sel=sel, out=muxef);
  Mux(a=a[1], b[1]=notSel, sel=sel, out=muxgh);
  Or(a[1]=muxef, b[1]=muxgh, out=out[1]);

[hdllearn]

I have the same problem with this code also

//This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/1/Mux16.hdl
/**
 * 16-bit multiplexor:
 * for i = 0, ..., 15:
 * if (sel = 0) out[i] = a[i], else out[i] = b[i]
 **/
CHIP Mux16 {
    IN a[16], b[16], sel;
    OUT out[16];

    PARTS:
    //// Replace this comment with your code.
    //// a and b are 16 bits data buses. out=a 16 bits bus
    Not(in=sel, out=notSel);

    And(a[0]=b[0], b[0]=sel, out=outand0);
    And(a[0]=a[0], b[0]=notSel, out=outand1);
    Or(a[0]=outand0, b[0]=outand1, out=out[0]);
   

    And(a[1]=b[1], b[1]=sel, out=out2);
    And(a[1]=a[1], b[1]=notSel, out=out3);
    Or(a[1]=out2, b[1]=out3, out=out[1]);


    And(a[2]=b[2], b[2]=sel, out=outand4);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[2]=a[2], b[2]=notSel, out=outand5);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[2]=outand4, b[2]=outand5, out=out[2]);



    And(a[3]=b[3], b[3]=sel, out=outand6);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[3]=a[3], b[3]=notSel, out=outand7);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[3]=outand6, b[3]=outand7, out=out[3]);

   
    And(a[4]=b[4], b[4]=sel, out=outand8);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[4]=a[4], b[4]=notSel, out=outand9);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[4]=outand8, b[4]=outand9, out=out[4]);



    And(a[5]=b[5], b[5]=sel, out=outand10);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[5]=a[0], b[5]=notSel, out=outand11);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[5]=outand10, b[5]=outand11, out=out[5]);



    And(a[6]=b[6], b[6]=sel, out=outand12);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[6]=a[6], b[6]=notSel, out=outand13);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[6]=outand12, b[6]=outand13, out=out[6]);



    And(a[7]=b[7], b[7]=sel, out=outand14);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[7]=a[7], b[7]=notSel, out=outand15);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[7]=outand14, b[7]=outand15, out=out[7]);


    And(a[8]=b[8], b[8]=sel, out=outand16);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[8]=a[8], b[8]=notSel, out=outand17);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[8]=outand16, b[8]=outand17, out=out[8]);


    And(a[9]=b[9], b[9]=sel, out=outand18);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[9]=a[9], b[9]=notSel, out=outand19);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[9]=outand18, b[9]=outand19, out=out[9]);



    And(a[10]=b[10], b[10]=sel, out=outand20);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[10]=a[10], b[10]=notSel, out=outand21);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[10]=outand20, b[0]=outand21, out=out[10]);



    And(a[11]=b[11], b[11]=sel, out=outand22);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[11]=a[11], b[11]=notSel, out=outand23);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[11]=outand22, b[11]=outand23, out=out[11]);


    And(a[12]=b[12], b[12]=sel, out=outand24);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[12]=a[12], b[12]=notSel, out=outand25);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[12]=outand24, b[12]=outand25, out=out[12]);


    And(a[13]=b[13], b[13]=sel, out=outand26);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[13]=a[13], b[13]=notSel, out=outand27);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[13]=outand26, b[13]=outand27, out=out[13]);



    And(a[14]=b[14], b[14]=sel, out=outand28);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[14]=a[14], b[14]=notSel, out=outand29);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[14]=outand28, b[14]=outand29, out=out[14]);


    And(a[15]=b[15], b[15]=sel, out=outand30);
    //case INPUT a[i]=/=b[i], b[i]=/=sel, out=a[i]
    And(a[15]=a[15], b[15]=notSel, out=outand31);
    //Either b=sel or a=sel i.e b=notSel
    Or(a[15]=outand30, b[15]=outand31, out=out[15]);


}

[WBahn]

hdllearn wrote

Not(in=sel, out=notSel);


   Mux(a=a[0], b[0]=sel, sel=sel, out=muxab);
   Mux(a=a[0], b[0]=notSel, sel=sel, out=muxcd);
   Or(a[1]=muxab, b[1]=muxcd, out=out[0]);



  Mux(a=a[1], b[1]=sel, sel=sel, out=muxef);
  Mux(a=a[1], b[1]=notSel, sel=sel, out=muxgh);
  Or(a[1]=muxef, b[1]=muxgh, out=out[1]);

This is the code for Mux16???

[WBahn]

Remember that pin assignments are of the form

<part_name>(<a pin of the part> = <a signal in the chip>, ...);

So consider the following line:

And(a[1]=b[1], b[1]=sel, out=out2);

You are connecting pin a[1] of the And gate to signal b[1] of your new chip.

But the And gate's 'a' signal is a 1-bit signal. So it consists of a[0] only. There IS no a[1] going into an And gate. For 1-bit signals, the signal name by itself or the signal name appended with [0] are synonomous.

[hdllearn]

yes this is my code for Mux16

[WBahn]

hdllearn wrote

yes this is my code for Mux16

So you aren't using input signal 'b' at all???

You are only using two of the sixteen bits in the 'a' input signal?

You are only driving two of the sixteen bits in the 'out' signal?

Your are setting the output to either one of the 'a' bits or to the 'sel' bit?

Read the description of what this chip is supposed to do.

[hdllearn]

Hi Bahn, I do not understand your point: CHIP Mux16 { IN a[16], b[16], sel; OUT out[16]; PARTS: //// Replace this comment with your code. //// a and b are 16 bits data buses. out=a 16 bits bus Not(in=sel, out=notSel); And(a[0]=b[0], b[0]=sel, out=outand0); And(a[0]=a[0], b[0]=notSel, out=outand1); Or(a[0]=outand0, b[0]=outand1, out=out[0]); //You are connecting pin a[1] of the And gate to signal b[1] of your new chip. And(a[1]=b[1], b[1]=sel, out=out2); And(a[1]=a[1], b[1]=notSel, out=out3); Or(a[1]=out2, b[1]=out3, out=out[1]); Can you please explain how I am connecting a[1] to b[1] ? How come a[1] does not exist?

[hdllearn]

   Hi WBAhn
Why does it work for a[0], b[0] ???

   Mux(a=a[0], b[0]=sel, sel=sel, out=muxab);
   Mux(a=a[0], b[0]=notSel, sel=sel, out=muxcd);
   Or(a[0]=muxab, b[0]=muxcd, out=out[0]);

[WBahn]

hdllearn wrote

Hi Bahn,
I do not understand your point:

CHIP Mux16 {
    IN a[16], b[16], sel;
    OUT out[16];

    PARTS:
    //// Replace this comment with your code.
    //// a and b are 16 bits data buses. out=a 16 bits bus
    Not(in=sel, out=notSel);

    And(a[0]=b[0], b[0]=sel, out=outand0);
    And(a[0]=a[0], b[0]=notSel, out=outand1);
    Or(a[0]=outand0, b[0]=outand1, out=out[0]);
   

    //You are connecting pin a[1] of the And gate to signal b[1] of your new chip.
    And(a[1]=b[1], b[1]=sel, out=out2);
    And(a[1]=a[1], b[1]=notSel, out=out3);
    Or(a[1]=out2, b[1]=out3, out=out[1]);



Can you please explain how I am connecting a[1] to b[1] ?
How come a[1] does not exist?

Let's look at one particular line:

    And(a[1]=b[1], b[1]=sel, out=out2);

The 'And' gate has two 1-bit inputs, named 'a' and 'b'. It also has a 1-bit output, named 'out'.

So when you use this part, it needs to look like the following:

    And(a=<some signal>, b=<some signal>, out=<some signal>);

The 'a', 'b', and 'out' names in the above line (i.e., names on the left side of an equals sign) refer to pins in the part being instantiated (which, in this case, is the 'And' part).

Look at the definition of the 'And' part in And.hdl:

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
    // Put your code here:
}

That is where the names come from for the signals on the left side of the equals sign when you use an 'And' gate. All three of these are 1-bit signals. Just like any bus (though we seldom think of bus as being 1-bit wide, but it's perfectly valid to do so), we can refer to all of the signals collectively by just using the name of the bus, or we can refer to a subset of it by using the subscript notation (i.e., square brackets).

So, for the 1-bit signal 'a' in the 'And' gate, we can refer to the entire thing, all 1 bit of it, with 'a', or we can refer to one of its individual elements using subscript notation using 'a[0]'. Both refer to the same 1-bit signal. We can't connect to 'a[1]' because that signal is not a part of the bus.

So that's the left side of the equals sign.

What appears on the right side of the equals sign are signals in the new chip that you are writing (Mux16, in this case). There, you have a signal named 'a', but it is a 16-bit signal. If you just use 'a' on the right side of an equals sign, you are saying to connect all 16-bits of the 'a' signal to the pin that is on the left side of the equals sign.

So if you have

And(a=a, ...);

You are trying to connect the 'And' gates 1-bit input named 'a' (the left side) to the Mux16's 16-bit input signal (the right side). This can't be done. You can only connect signals of the same width.

Since you can't do anything about the width of the 'And' gate's 'a' input, you have to pick a 1-bit signal from among the 16 signals that make up the Mux16's 'a' input signal.

So you do

And(a=a[0],...);
And(a=a[1],...);

and so on.

The key is to understand that which signal a name is referring to depends on where that name appears. If it is on the left sign of an equals sign, it is ALWAYS referring to one of that part's pin names. That is also the ONLY place that that name refers to a part's pin names.

If it is on the right side of an equals sign, it is ALWAYS a signal for the new chip being defined, though it may be an input or output signal, or just an internal signal used to connect parts together.

[hdllearn]

Thanks Bahn

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