Mux4Way16

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Re: Mux4Way16

WBahn
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This post was updated on .
Good.

So, what could you do to get a signal that is 1 if and only if sel[0] and sel[1] are 0.

Hint, think about how you would say it if you could only describe it in English using 1 (and not 0) in your description. For instance, you can't say, "If x is 0", but you can say, "If x is not 1". You also can't use terms like "both" or "either", but you can say things like, "If (something) and (something)", or, "If (something) or (something)".

So translate the statement "If both sel[0] and sel[1] are 0" into an equivalent sentence subject to the above constraints.


Spoiler. To some degree, this discussion is going down a bit of a rabbit hole because there is a very simple way to implement this chip, based on the cereal dispenser analogy I gave above. None-the-less, it looks like it will still be worthwhile to help you build your reasoning skills regarding digital logic.
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Re: Mux4Way16

hdllearn
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yes I need to learn
John
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Re: Mux4Way16

hdllearn
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/1/Mux4Way16.hdl
/**
 * 4-way 16-bit multiplexor:
 * out = a if sel = 00
 *       b if sel = 01
 *       c if sel = 10
 *       d if sel = 11
 */

 /**Algo for building gates:
 1. Understand Truth table
 2. Do logical flow of BITS with basic logic or previously built logic gates.
 3. Fix portion/ story paragraph by paragraph with testing and comparing with output to Truth table desired.
 4. Test final 'out' result. Fix any bug in flow of bits logic.
 5. NB: for each paragraph of code draw the truth table and check if the output gives the correct answer for all possibilities of input pins.
 6. NB: Check code paragraph as written not as you wish it or assume it eill work.
 **/
CHIP Mux4Way16 {
    IN a[16], b[16], c[16], d[16], sel[2];
    OUT out[16];
   
    PARTS:
    ////And, Or, Not, Xor, Mux, Mux16, And16, Or16, Not16
    //// Replace this comment with your code.
   
    //00. outand7=0. This code is wrong as 00, 10, 01 will give 1 as output.
    //Algo:
    //Good.
    /**
So, what could you do to get a signal that is 1 if and only if sel[0] and sel[1] are 0.
Hint, think about how you would say it if you could only describe it in English using 1 (and not 0) in your description.
 For instance, you can say, "If x is 0", but you can say, "If x is not 1". You also can't use terms like "both" or "either",
 but you can say things like, "If (thing) and (something)", or, "If (something) or (something)".
 So translate the statement "If both sel[0] and sel[1] are 0" into an equivalent sentence subject to the above constraints.
 Spoiler. To some degree, this discussion is going down a bit of a rabbit hole because there is a very simple way to implement this chip,
 based on the cereal dispenser analogy I gave above. None-the-less, it looks like it will still be worthwhile to help you build your reasoning
  skills regarding digital logic.
*/

/*
Algo to determine sel[2]=00 : IFF BOTH sel[0]=0 and sel[1]=0 return 0, that is true:
problem: sel[0]=1 and sel[1]=1 will also return 1
         sel[0]=0 and sel[1]=0 will also return 1

Truth table:
a    b   And   Or   Nor  Xor     ?     ?
0    0   0     0     1           0     1
0    1   0     1     0    1      0     1
1    0   0     1     0    1      1     0
1    1   1     1     0           0     1
*/
Or(a=sel[0], b=sel[1], out=outor);
Not(in=outor, out=out00);

/**
Algo to determine sel[2] = 11
IFF sel[0]=1 and sel[1]=1 return 1, that is true. See Truth table above.
**/
And(a=sel[0], b=sel[1], out=out11);


/*
Algo to determine sel[2]=10
IFF sel[0]=1 and sel[1]=0 return 1

Truth table:

a   b  Notb   And(a, notb)
0   0   1        0
0   1   0        0
1   0   1        1
1   1   0        0

nb: when program loads it sets sel[2]=00. Therefore notsel1=1. Hence when changing sel[2] to 10, notsel1(1) =0.
*/
Not(in=sel[1], out=notsel1);
And(a=sel[0], b=sel[1], out=out10);

}

I have a problem with the Not(in=sel[1], out=notsel1).
When I load the chip in HardwareSimulator the sel[2]=00 by default, which sets notsel1 to 1. So when I change the sel[2] to 10 and run the program again it gives me notsel1=0. Which does not give me the result i expected that is '1' for And(sel[0], b=notsel[1], out=out10);

Can you please advise how I can overcome this issue?

Thanks in advance
John
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Re: Mux4Way16

WBahn
Administrator
hdllearn wrote
Truth table:
a    b   And   Or   Nor  Xor     ?     ?
0    0   0     0     1           0     1
0    1   0     1     0    1      0     1
1    0   0     1     0    1      1     0
1    1   1     1     0           0     1
*/
Or(a=sel[0], b=sel[1], out=outor);
Not(in=outor, out=out00);
This works (for sel = 00) and is just fine. But let's see what we get if we translate the English description of what we want according to the rules I suggested, and then walk that little by little toward syntactically correct Hack HDL code:

out00 should be 1 when both sel[0] and sel[1] are 0.

out00 is 1 when (sel[0] is 0) AND (sel[1] is 0).

out00 is 1 when (sel[0] is NOT 1) AND (sel[1] is NOT 1).

out00 is 1 when (NOT(sel[0]) is 1) AND (NOT(sel[1]) is 1).

out00 is 1 when (NOT(sel[0]) AND (NOT(sel[1])).

out00 = (NOT(sel[0]) AND (NOT(sel[1]))

out00 = AND( NOT(sel[0]), NOT(sel[1]) )

notsel0 = NOT(sel[0])
notsel1 = NOT(sel[1])
out00 = AND(notsel0, notsel1)

Not(in = sel[0], out = notsel0);
Not(in = sel[1], out = notsel1);
And(a = notsel0, b = notsel1, out=out00);


A couple of other suggestions:

First, don't use sel[2] to refer to the entire sel signal. That is going to cause all kinds of confusion since people will tend to think you are talking about a third 1-bit signal in the sel signal, which doesn't exist. The ONLY time sel[n] is used to refer to the entire bus, is in the IN and OUT statements of a chip, and in that context, the value in brackets can only represent the total number of signals in the bus.

Second, use the raw code tags (you can either type them directly, or use the "Raw text" option from the "More" dropdown list.

Example:

Truth table:
a b And Or Nor Xor ? ?
0 0   0  0   1     0 1
0 1   0  1   0   1 0 1
1 0   0  1   0   1 1 0
1 1   1  1   0     0 1

Note that I preserved the two missing 0 entries from your Xor column.

Since your browser probably insists on using a proportional-spaced font while you edit your post, you can either use the "Preview Message" button to verify that the alignment is what you want, or open up a text editor that uses a monospaced-font and layout your content there and then copy/paste it into the post.
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Re: Mux4Way16

hdllearn
Hi WBahn

I am sorry to bother you, but I do not understand your explanation. Can you please re-explain?

Thanks
John
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Re: Mux4Way16

WBahn
Administrator
I assume you are talking about the explanation of going from an English sentence to a logic circuit?

The basic idea is that our logic circuits are based on "positive logic", meaning that it refers to the relationship when things are True (or 1).

z = x AND y

means

(z is True) when (x is True) and (y is True)

z = x OR y

(z is True) when (x is True) or (y is True) (NOTE: Talking about Inclusive-OR here)

z = NOT x

means

(z is True) when (x is not True)

But we can go the other way. If you can get something to the form

(c is True) when (f is True) and (h is True)

then you can translate that directly into the logic equation

c = f AND h

So, in our case,

(out00 is True) when (sel[0] is not True) and (sel[1] is not True).

The phrase

(sel[0] is not True)

is translated to

NOT sel[0]

Similarly, the phrase

(sel[1] is not True)

is translated to

NOT sel[0]

So now we have

(out00 is True) when (NOT sel[0]) and (NOT sel[1])

Now we translate this using the pattern for AND, to get

out00 = (NOT sel[0]) AND (NOT sel[1])

Everything else is just translating things to the particular syntax of the Hack HDL.



 
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Re: Mux4Way16

hdllearn
No. What I do not understand is that HDL language is not a programming language but a descriptive definition language:
I do not understand how to solve the issue in my following code. When the HardwareSimulator is run, it set the sel by default to sel=00. So it seems that it runs my code and sets not(sel[1]) =1. Then when I change the sel to sel=10 and rerun the HardwareSimulator, the not(sel[1]) is set to 0. Which is a problem since I am using And(a=sel[0], b=notsel1) which gives me 0 and not 1 as I defined it.

/*
Algo to determine sel[2]=10
IFF sel[0]=1 and sel[1]=0 return 1

Truth table:

a   b  Notb   And(a, notb)
0   0   1        0
0   1   0        0
1   0   1        1
1   1   0        0

nb: when program loads it sets sel[2]=00. Therefore notsel1=1. Hence when changing sel[2] to 10, notsel1(1) =0.
*/
Not(in=sel[1], out=notsel1);
And(a=sel[0], b=sel[1], out=out10);

}

I have a problem with the Not(in=sel[1], out=notsel1).
When I load the chip in HardwareSimulator the sel[2]=00 by default, which sets notsel1 to 1. So when I change the sel[2] to 10 and run the program again it gives me notsel1=0. Which does not give me the result i expected that is '1' for And(sel[0], b=notsel[1], out=out10);

Can you please advise how I can overcome this issue?
 
John
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Re: Mux4Way16

WBahn
Administrator
You are correct that HDL is NOT a programming language. It describes how various logic gates are connected. Think of it as describing how the circuit breaker panel in your house is connected to light switches and lights in your house. It is only describing the physical connections.

Once described, the connects behave like they behave. If a switch is turned on, the light connected to it turns on. If it is turned off, the light connected to it turns off. There is no "running the program" involved.

Because of that, there is no ordering requirement for the lines in the PARTS: section of your chip definition, because each line is merely describing how the pins of the various parts are connected together (and to the input/output pins of the overall chip being defined).

So your 'notsel1' signal is, at all times, equal to the opposite of what the sel[1] signal happens to be at that time. The 'notsel1' is NOT a variable that you store something in for later use. In a physical circuit, it would be a wire whose voltage is, at any moment in time, determined by the part whose output is connected to that wire.


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Re: Mux4Way16

hdllearn
Thanks WBahn. Now I understand why my code is not behaving as I expected.

Is there any software I can use to draw the electrical circuits to build the gates from atomic gates?

Thanks.
John
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Re: Mux4Way16

WBahn
Administrator
hdllearn wrote
Thanks WBahn. Now I understand why my code is not behaving as I expected.

Is there any software I can use to draw the electrical circuits to build the gates from atomic gates?

Thanks.
Yes, though it depends on if you are just wanting to draw the circuits so that you can visualize the connections, or if you want to actually simulate their functionality. Software exists for both, with most of them being better at one versus the other.

The one I am currently working with is Digital (which is actually a pretty poor name for a program in the age of web search engines). It has quite a bit going for it, but some significant downsides, as well. It's nice for interactive simulations, but it doesn't appear able to produce traces of behavior over time (similar to a logic analyzer).

 
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Re: Mux4Way16

hdllearn
Hi WBahn Good morning. I am trying to draw out the circuit for Mux8Way16. However I do not know how to connect the SELECTOR component. I cannot find any documentation on how to connect it. Attached is my digital file. Please Help!
John
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Re: Mux4Way16

hdllearn
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Re: Mux4Way16

hdllearn
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Re: Mux4Way16

WBahn
Administrator
In reply to this post by hdllearn
hdllearn wrote
Hi WBahn

Good morning. I am trying to draw out the circuit for Mux8Way16.

However I do not know how to connect the SELECTOR component. I cannot find any documentation on how to connect it.
I don't know what software you are using (Digital?).

I've never seen that Bit Selector component, but I just took a look at it and here is my best guess.

You bring a multibit bus into the input (left side) and then a select signal into the bottom of it. If your input signal is, say, 16-bits wide, then you need the select signal to be 4-bits wide, which you configure by right-clicking the component and putting that in the "Number of Selector Bits" box. The output is then a single bit that is chosen from the input bit based on the value on the select input.

That's a guess, as I haven't played with it.

Leaving that aside, consider your use of an OR gate to combine the outputs. Remember that an OR gate outputs a 1 if EITHER of its inputs are a 1. Is that going to meet your needs?
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Re: Mux4Way16

WBahn
Administrator
In reply to this post by hdllearn
I just played with the Bit Selector part in Digital and it looks like my guess was correct.



I definitely agree that the documentation for Digital leaves a LOT to be desired.
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Re: Mux4Way16

hdllearn
Hi WBahn

thanks for the diagram. But where do you get the connector for the 8way bus and 3 way bus please. I could not find it in components menu.

Please advise.

Thanks.
John
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Re: Mux4Way16

hdllearn
ok got it. thanks
John
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Re: Mux4Way16

hdllearn
I got a problem with the bit selector. I cannot select a 16 bit selection. Please help


John
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Re: Mux4Way16

hdllearn
Hi WBahn

I have tried the following way, but I have 2 selectors instead of 1 selector with 2 bits. Please advis

John
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Re: Mux4Way16

WBahn
Administrator
In reply to this post by hdllearn
hdllearn wrote
I got a problem with the bit selector. I cannot select a 16 bit selection. Please help
You need to configure your Splitter/Merger part by right clicking it. In the Basic tab, you specify how many bits are in each tap on the input and on the output tab.



In this case, the first four inputs, 0-3, are on the top tap, then the next two, 4,5, then the last two, 6,7. On the output, the first tap has the first six, 0-5, and the bottom one has just one, 6. The final input signal isn't ported out, indicating that the number of input and output taps don't need to be the same.

If you are tapping out multiple groups of the same size, you can use a shorthand notation width*n, saying that the next n taps are each of the given width. So to bring in 8 signals separately and combine them into a single bus, the Input Splitting could be either '1,1,1,1,1,1,1,1', or it could be simple, '1*8'.

The 'Advanced' tab controls the usual mirroring and rotation, but also the spacing between taps.
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