Need help with the conditions for load pin of the PC

[nirflysher]

I wonder if it is possible to have some tip of how to create the logic for the load pin of the PC in the CPU.hdl.
I know it has to use the j1,j2,j3 bits from the C-command and the ZR,NG outputs of the ALU.
It seems like the load pin is a function of 5 bits a fact that complicates the implementation.
For example : (j1,j2,j3)=0,0,1 ; (ZR,NG)=0,0  --> Load=1.  
Should i just implement the logic for each line of fig 4.5 (p.69) or is there a better implementation ?

[cadet1620]

nirflysher wrote

I wonder if it is possible to have some tip of how to create the logic for the load pin of the PC in the CPU.hdl.
I know it has to use the j1,j2,j3 bits from the C-command and the ZR,NG outputs of the ALU.
It seems like the load pin is a function of 5 bits a fact that complicates the implementation.
For example : (j1,j2,j3)=0,0,1 ; (ZR,NG)=0,0  --> Load=1.  
Should i just implement the logic for each line of fig 4.5 (p.69) or is there a better implementation ?

Sometimes adding more hardware ends up making the solution easier. Consider generating a PS (positive) status flag from the ZR and NG status flags. Add a column for the PS flag to the truth table for Load so that you have 6 inputs instead of 5. This should show a fairly easy to implement solution.

If you don't see it, be sure to ask for more help.

--Mark

[nirflysher]

Hi Mark,

Thanks for the tip.
I think i got it right.
The part i missed was the little notes in brackets just below the j1 j2 j3 on fig 4.5.


Thanks a lot !

A little tip for the next generations. Think simple, define the positive,negative,equal,grater and smaller  signals as Mark suggested and imagine a DMux8way...

Nir.