On sub-busing internal pins to determine ng and zr

[PLV]

When implementing zr and ng, I don't know of a way to do it without sub-busing internal pins, that is, without selecting output[0..7] from output[16]; this seems to be an issue regarding the way that HDL was designed rather than a real-world limitation--only input pins can be sub-bused--though I am a beginner at this and I might be wrong. It stumped me for a little while until I realized that I could make a seperate chip with in[16] and out[1] or out[8] or whatever is needed, and then using that chip in the ALU.hdl file instead of implementing the logic directly on the ALU...abstraction and all that.

Just a heads up to anyone else that may come across this issue.

[cadet1620]

Carefully read appendix A.5.3 and study the example and you will see that you can make multiple connections to a part's output -- a part can have more than one "out=" connection. This corresponds to soldering more that one wire to an output in the real-world.

The same part that generates the ALU's output can also create all the various sub-buses that you want:
    SomePart(..., out=out, out[0..7]=lowBits, ... );

--Mark

[MultiplexorMan]

@cadet1620

Thank you! Your comment was the lightbulb comment for me. I was able to pass the ALU-nostat tests but was stuck on the ALU tests for zr and ng.