Output width of CPU PC showing up as 15 bits instead of 16.

[kraftwerk1611]

Hi all,

I am trying to implement CPU.hdl and when I run my solution with this line.

PC(in=AandM, load=jump, inc=true, reset=reset, out=pc);

I get the following error message.



The input AndM is coming from built-in ARegister and it is 16 bits.

Can someone please point out to me my mistake.

Thanks.

[cadet1620]

In its I/O specification (at the top of the HDL) PC is declared as PC[15], so you need to connect only the PC part's out bits 0-14 to PC.

You will need to make a similar connection for addressM which is also declared as 15 bits wide.

--Mark

[kraftwerk1611]

Thank you.

Yes it works that way, the address in memory 15 bits.
 

But why Builtin PC chips spec says that both input and output are 16 bits? Sorry if it obvious

CHIP PC {

    IN  in[16], load, inc, reset;
    OUT out[16];

    BUILTIN PC;
    CLOCKED in, load, inc, reset;
}

[cadet1620]

I'm guessing that PC is specified as 16 bits wide so that it is more general purpose. It would be possible to use it in a Hack-like computer that had 64K of ROM.

The Hack computer only has 32K of ROM because it is difficult to jump to address > 32K since the "@" instruction only holds 15-bits of data.

--Mark

[kraftwerk1611]

Thank you for clarifying it.