PC logic changed?

[Marty Billingsley]

In previous versions of Project 3, the PC logic in PC.hdl was described as:
/**
 * A 16-bit counter with load and reset control bits.
 * if      (reset[t] == 1) out[t+1] = 0
 * else if (load[t] == 1)  out[t+1] = in[t]
 * else if (inc[t] == 1)   out[t+1] = out[t] + 1  (integer addition)
 * else                    out[t+1] = out[t]
 */

In the nand2tetris software downloaded in Jan 2024, the logic in PC.hdl is described as:
/**
 * A 16-bit counter with increment, load, and reset modes.
 * if      (inc(t))   out(t+1) = out(t) + 1
 * else if (load(t))  out(t+1) = in(t)
 * else if (reset(t)) out(t+1) = 0
 * else               out(t+1) = out(t)
 *
 * To select a mode, assert the relevant control bit,
 * and de-assert the other two bits.
 */

Obviously this changes the way the PC should be implemented. Why the change? Doesn't reset still trump everything else? It also doesn't look as if the .tst script was changed to match, which is causing my students to run into errors.

Edition 2 of the book (p55) states the PC logic as the same as in edition 1 (p51).

[WBahn]

I don't know why the comments at the beginning of the PC.hdl file were changed, but the book is correct and the test files are consistent with the book.

[Marty Billingsley]

Thanks. Any other changes to .hdl files that I should be on the lookout for?