Processor vs RAM performance

[moejoe125]

Now that I've completed the ALU and Memory chips from the 2nd and 3rd chapters, I'm starting to wonder what inherently makes memory access so much slower than the CPU operations.

Is it just the sheer number of address bits that need to be set on all of the MUXs to access a particular memory word per cycle?

[cadet1620]

There is a lot of complexity in large RAMs. I'm not up to date on physical implementation of modern RAMS, but in general most large RAMs use dynamic memory cells which are much smaller that storage cells built around logic gates.

Dynamic memory uses small capacitors to hold the data. The problem with this is twofold. Some of the charge stored in the capacitors is lost every time the bit is read, and the capacitors self-discharge over time. This means that the bits must be rewritten after reading and be periodically rewritten even if they are never read.

In each dynamic RAM chip there is a control circuit that manages this read/rewrite requirement. The RAM chips that I designed with required external circuits to tell them when to do the periodic refreshes. I've read that there are self-refreshing RAMs available now but know nothing about them.

Electrically, there is a feature that is not available in the n2t simulator that helps eliminate a lot of the output multiplexing circuitry. Wires can carry 0 and 1 signals and can also be in an "open" state when no value is driven on the wire.  If all the memory cells' outputs are in this open state except for the cell that is being read, they can be directly connected together. There is an implementation dependent limitation on the number of outputs that can be connected together this way.

--Mark