Prolog implementation

[Sunomis]

Hi!

I hope this is the right thread for posting this. I've been having fun testing my designs on Prolog, additionally to the platform provided with the course.

So far, I've been able to implement my ALU on Prolog, but I wonder how I could go about doing the memory part. The problem, of course, to simulate the ticking of the clock.

I'm only just a beginner at Prolog, so I may be way off, but is it possible to run the ALU

1- while an endless recursive loop is running (to simulate the clock)
2- and still be able to access / communicate with it ?

Thanks for you help!

[burge91]

Does Prolog support Threading? If so it'll be a simple case of flipping a bit every T milliseconds and feeding it to every sequential gate. So you'd just need a while loop with a Thread.wait(500) or something I think, flipping a global boolean after each Wait completes.

I always thought the hardest thing about this was to simulate the DFF not the clock?? (but I'm not using Prolog). I tried to do that via some animation software but haven't really made progress.

[ivant]

My Prolog skills are very rusty. Last time I played with it was around 1995 I think.

In any case it shouldn't be too hard to simulate the clock as a parameter to sequential circuit, with values TICK (or RISING), meaning the clock value is changing from 0 to 1, TOCK (or FALLING) for when the value is changing from 1 to 0. The clock should only be changing in the main "loop"; all other gates and circuits should just pass it through. DFFs should be the only gates which do care about the clock's value.

[cadet1620]

Note that Ivan's solution is calling the DFF objects' clock function twice per clock cycle. clock(TICK) stores the input value in the object. clock(TOCK) copies the stored value to the output.

This is how the HardwareSimulator implements DFF (it actually has two functions: clockUp and clockDown).

--Mark