Question about Add16

[Lindy]

I finally got this to work (I hope I got it right), and it was my first time to see two numbers being added together just using logic gates.  That was fun.

When I was playing with it, I noticed that I created an extra carry out pin which I could use to test for a numeric overflow.  Or I could stack multiple Add16's to add 64 bit numbers.

So my question is this.  At this level in the chip, is it useful to know if that last carry bit is set?  

thanks for your help!
Lindy

[cadet1620]

Lindy wrote

When I was playing with it, I noticed that I created an extra carry out pin which I could use to test for a numeric overflow.  Or I could stack multiple Add16's to add 64 bit numbers.

So my question is this.  At this level in the chip, is it useful to know if that last carry bit is set?  

If you use a full adder for bit 0 and connect its carry-in to an Add16 carry-in input, you can cascade Add16s like you cascade FullAdders.  In fact, in the hardware serries I worked the most with in the 70s, the basic adder chip was 4 bits wide so we cascaded 4 of them to make a 16-bit adder.

Detecting numeric overflow in 2's-complement is a bit trickier that just looking at the final carry out. Consider adding -1 and -1: there will be a carry out, but the result, -2, is a valid number so there was no overflow.

To detect overflow in the Add16 you need to note that the carry-in to bit 15 is different from the carry-out from bit 15.
    FullAdder(a=a[15], b=b[15], c=carry14, out=out[15], carry=carry15, carry=carry);
    Xor(carry14, carry15, out=overflow);
assuming additional Add16 outputs carry and overflow.

--Mark

[Lindy]

Would you mind helping me a bit just to get started?  This is the first time I've tried to make something with a bus in it.  I got this far and gave up.  :-)

CHIP Add64 {
    IN a[64], b[64];
    OUT out[64];

    PARTS:
    FullAdder(a=a[0],  b=b[0],  c=false,  sum=s1,  carry=c1);
   
    Add16(a=a[1..16], b=

Or, do I need to add that extra pin for the carry out on my Add16?  

Thanks!
Lindy

[cadet1620]

I'm pretty sure that the HW simulator won't handle buses wider than 16 bits without crashing. If you want to experiment with more complicated logic, I'd suggest checking out Logisim. (Note that Logisim is limited to 32-bit buses.)

That said, assuming that you had an Add16 that had
    INPUT
        a[16], b[16], c;
    OUTPUT
        out[16], carry;
you would want Add64's PARTS to be
    Add16(a=a[0..15], b=b[0..15], c=false, out=out[0..15], carry=c0);
    Add16(a=a[16..31], b=b[16..31], c=c0, out=out[16..31], carry=c1);
    Add16(a=a[32..47], b=b[32..47], c=c1, out=out[32..47], carry=c2);
    Add16(a=a[48..63], b=b[48..63], c=c2, out=out[48..63]);

--Mark