Question about D-Flip Flop again

[kqian]

What would happen if I store/load and then read from a register within the same clock cycle. This would give me the value from the previous clock cycle which is incorrect. Is there something within the DFF that stops this from happening?

[cadet1620]

See this response to "Question about clock".

[cadet1620]

Real hardware is full of tricky timing problems like this. If you try to do something too soon after something else, undefined behavior occurs! One of the engineer's jobs is to ensure that all the hardware timing requirements are respected.

--Mark

[kqian]

Thanks for the reply. I wonder how engineers solve problems like this in the real hardware. Where can I read more about it?

[cadet1620]

kqian wrote

Thanks for the reply. I wonder how engineers solve problems like this in the real hardware. Where can I read more about it?

For an example of a timing problem in hardware and how to mitigate it, see my page on hazards.

Here's a sample DFF IC datasheet.

A quick search didn't turn up any free ebooks on digital design. You might try searching google books for terms like "microelectronic design". If you find a book that looks interesting, try searching for an older edition using bookfinder.com. It often turns up cheap copies of older books.

--Mark