Question about DFF chip and Clock

[Adam]

Hello - with the DFF chip, when exactly does changing the input and the output registering it occur with regards to the clock cycle 0 0+ 1 1+ etc.

For example, if the time is 0 and I set Value=1, then out will change to 1 when the time is 1.

However, if the time is 0+ and I set Value=1, then out will change to 1 only when the time is 2.

In other words, it seems the n+ times don't really do anything?

Relating to this - how does the 0 0+ 1 1+ etc. format correspond with the 0 1 0 1 0 1 etc. format given in the book (second edition) (I assume just n is 0 and n+ is 1?), and how do these 0s and 1s correspond to a time 't' as used in the API for chips such as the DFF. I.e., we say the DFF chip has the abstraction out[t]=in[t-1], but which t is this referring to? The n or n+? Or both? And if both... how?

Any help would be appreciated. Thanks!

[WBahn]

I'm not sure that I understand your questions well enough to answer them properly, but perhaps this will help.

Ignoring the N2T project and simulation for the time being, nearly all DFFs are edge-sensitive devices the behave as follows (assuming that they are positive-edge sensitive, which is the most common):

The data on the D input has to be established and stable a short time before the rising edge of the clock. This is known as the set up time. That value has to be held constant until a short time after the rising edge. This is known as the hold time. In other words, the data value that is being captured has to be stable and constant for a small window of time on both sides of the clock edge.

The data value that is captured at the rising clock edge appears at the output of the DFF a short amount of time later. This is known as the propagation delay.

In a properly designed DFF, the hold time is significantly shorter than the propagation delay. Thus, if the output is passed back to the input (probably through some logic), by the time that the new value of the output reaches the input, the flip flop is no longer sensitive to changes in the input for that clock cycle.

Switching gears back to N2T, with the DFF description says that out[t] = in[t-1], all this is saying is that the output of the DFF at the end of each clock cycle is equal to whatever value the signal was at its input at the end of the prior clock cycle.

As far as the Hardware Simulator is concerned, the whole tick/tock and 0 0+ 1 thing is simply the method by which the authors chose to model this behavior. On the tick, the inputs of the chip are evaluated and the value that will eventually appear on the output pin is determined. On the tock, the output pins are updated with the new value. The + essentially means the value on the output pins a short time (the propagation delay) after the clock edge.