Question about clock

[kqian]

I have noticed that in the test script for Register.hdl that every time there is a load be it 0 or 1 the clock will tick. Is this a function of the clock?

[cadet1620]

kqian wrote

I have noticed that in the test script for Register.hdl that every time there is a load be it 0 or 1 the clock will tick. Is this a function of the clock?

Register is a synchronous circuit. Changing "in" and "load" doesn't cause any change in the DFFs the Register is built from. The DFFs only change when the clock ticks.

--Mark

[kqian]

Is it possible for two instructions to be processed before the next tick occurs? If this happens wouldn't the wrong value be loaded into the output? For example:

| time |   in      |load |  out   |
| 0+   |      0    |  0  |      0 |
| 1     |      0    |  0  |      0 |
| 1+   |      0    |  1  |      0 |
| 2     |      0    |  1  |      0 |
| 2+   | -32123 |  0  |      0 |
| 3     | -32123 |  0  |      0 |
| 3+   |  11111 |  1  |      0 |
| 3+   |  11111 |  0  |      0 | //here the register is asked to output the previously loaded value which is 11111 but outputs 0. The next tick didn't occur yet.

This seems possible in theory, but perhaps I am misunderstanding how the clock and DFF interacts.

[cadet1620]

What you are seeing is that the Hardware Simulator's DFFs function as master-slave flip-flops, which are subtly different from truly edge triggered flip flops.

When the clock ticks, the input value is saved in the DFF's master stage. When the clock tocks, the master stage is copied to the slave stage. The slave stage is connected to the DFF's output.

    

(1) Load is true when clock ticks. Internal state (master stage) is set from input.
(2) Load goes false. The DFF state doesn't change since the clock doesn't change.
(3) Clock tocks; Output (slave stage) set from internal state.
(4) Master stage updated with new input value when clock ticks. Output doesn't change.

// Register.tst:
output;
set in 42, set load 0, tick, output;
tock, output;
set in 42, set load 1, tick, output;
tock, output;
set in -32123, set load 0, tick, output;
tock, output; 
set in 11111, set load 1, tick, output;    // (1)
set load 0, output;                        // (2)
tock, output;                              // (3)
set in -32123, set load 1, tick, output;   // (4)
tock, output;

output:

| time |   in   |load |  out   |
| 0    |      0 |  0  |      0 |
| 0+   |     42 |  0  |      0 |
| 1    |     42 |  0  |      0 |
| 1+   |     42 |  1  |      0 |
| 2    |     42 |  1  |     42 |
| 2+   | -32123 |  0  |     42 |
| 3    | -32123 |  0  |     42 |    (1)
| 3+   |  11111 |  1  |     42 |    (2)
| 3+   |  11111 |  0  |     42 |    (3)
| 4    |  11111 |  0  |  11111 |    (4)
| 4+   | -32123 |  1  |  11111 |
| 5    | -32123 |  1  | -32123 |
| 5+   | -32123 |  1  | -32123 |
| 6    | -32123 |  1  | -32123 |
| 6+   | -32123 |  0  | -32123 |
| 7    | -32123 |  0  | -32123 |
| 7+   |  12345 |  1  | -32123 |
| 8    |  12345 |  1  |  12345 |
| 8+   |      0 |  0  |  12345 |
| 9    |      0 |  0  |  12345 |

--Mark