RAM 64

[Efof]

Hi,

I have designed the RAM64, but for some reason when I am running the test the content of the address 47 is erased when I am writing in the address 63.  I have tried to debug it without success. So, I don't arrive to figure out what I have done wrong. Can somebody help me please?
Here is my implementation:
CHIP RAM64 {
    IN in[16], load, address[6];
    OUT out[16];

    PARTS:
    DMux8Way16(in=in, sel=address[3..5],a=inRAM0, b=inRAM1, c=inRAM2, d=inRAM3, e=inRAM4, f=inRAM5, g=inRAM6, h=inRAM7);
        RAM8(in=inRAM0, load=load, address=address[0..2], out=outRAM0);  // @ 0 to 7
        RAM8(in=inRAM1, load=load, address=address[0..2], out=outRAM1);  // @ 8 to 15
        RAM8(in=inRAM2, load=load, address=address[0..2], out=outRAM2);  // @16 to 23
        RAM8(in=inRAM3, load=load, address=address[0..2], out=outRAM3);  // @24 to 31
        RAM8(in=inRAM4, load=load, address=address[0..2], out=outRAM4);  // @32 to 39
        RAM8(in=inRAM5, load=load, address=address[0..2], out=outRAM5);  // @40 to 47
        RAM8(in=inRAM6, load=load, address=address[0..2], out=outRAM6);  // @48 to 55
        RAM8(in=inRAM7, load=load, address=address[0..2], out=outRAM7);  // @56 to 63
        Mux8Way16(a=outRAM0, b=outRAM1, c=outRAM2, d=outRAM3, e=outRAM4, f=outRAM5, g=outRAM6, h=outRAM7, sel=address[3..5], out=out);
}

Thank you.

[cadet1620]

In your design, whenever the RAM64's load is true, all the RAM8s store whatever is on their input. Think about what you need to do to only load a single RAM8.

--Mark

[Efof]

That's right I had the same problem when I have designed the RAM8 before; that I have solved with a DMux8Way to control the Register load. So, I have done the same for the RAM64 to control the RAM8 load.

Thank you!

[cadet1620]

Note that you don't need to DMux8Way16 the in bus. Do you see why?

--Mark

[Efof]

Yes I see it! :-) Because, it is the token which determines which RAM cell will store the data.
Thank you for the hint!

E.