Register.hdl

[tyler1313]

In Register.hdl, the Register has 17 inputs and 16 outputs.

CHIP Register {
    IN in[16], load;
    OUT out[16];
    ...


However in RAM8.hdl, 8 Registers are laid out with only 2 inputs each. How is this possible? Is it because the "in" defined for each register is actually in[0-15], so 16 wires defined as just "in"? In this case out1, out2, etc would also be 16 wires?

CHIP RAM8 {
    IN in[16], load, address[3];
    OUT out[16];

    PARTS:
    // RAM8 will consist of 8 16-bit registers.
    // each register's input is directly connected to the RAM's input
    Register(in=in, load=load1, out=out1);
    Register(in=in, load=load2, out=out2);
    ...

[cadet1620]

It is better to think that Register has 2 inputs and 1 output. One of the inputs is "in[16]", meaning a bus with 16 wires. "out[16]" is also 16-bit bus.

RAM8 has the same "in" and "out" 16-bit buses.

When you write "Register(in=in" you are connecting the Register's "in" bus to the RAM8's "in" bus. If you want to be explicit, you can connect all 16 wires to the matching 16 wires using sub-bus syntax: "Register(in[0..15]=in[0..15]".

Yes, "Register(... out=out1)" creates a 16-bit bus named "out1". In general, the width of new wire/bus on the right side of "=" matches the width of the left side. For example, "out[0..3]=four" will create a 4-bit bus named "four".

--Mark

[tyler1313]

Thanks for the explanation, that was helpful.