Suggestion: think binary!

[gs99]

When I completed DMUX4WAY and DMUX8WAY in chapter 1, they worked.
But when I came to RAMxxx in Chapter 3a, I realized the need to think binary, and I went back to redo those two chips.

Example: In RAM64 we need to process 64 addresses, arranged in 8 RAM8s of 8 Registers each.
My initial thought was decimal and sequential:
Register 1 will have addresses 0 to 7.
Register 2 addresses 8 to 15...
Register 8 addresses 56 to 63.

But that's not how binary works.
There's no need for the addresses to be sequential.
Register 1 will be associated with addresses 0, 8, 16, 24, 32, 40, 48, and 56.
Register 2 addresses 1, 9,  17, 25, 33, 41, 49, and 57...
Register 8 addresses 7, 15, 23, 31, 39, 47, 55, and 63.

You need to see the binary equivalents to appreciate the patterns.
The hdl needs to recognize the binary patterns of parts of the address (e.g. sel[0..2]).

Getting back to DMUX4WAY and DMUX8WAY.
My original hdl worked; they passed the script test OK.
But I simplified them to be organized more like RAMxxx hdl.

Perhaps this will help someone.
Write it visually to see what happens with each address.