Trouble with ng and zr in ALU

[Cardinal]

Hi, I'm having trouble with getting the ng and zr chips to match up with ALU.tst. My script is producing the correct output, and I've taken ng to be the leftmost bit of the out. I'm then taking an Or8Way between the first 8 bits of out, another one between the last 8 bits of out, and feeding each of those outs into a Or. I'm pretty sure this is what I'm supposed to be doing. I've checked my code for bugs over and over again, but I just can't see what the problem is.

[cadet1620]

Cardinal wrote

Hi, I'm having trouble with getting the ng and zr chips to match up with ALU.tst. My script is producing the correct output, and I've taken ng to be the leftmost bit of the out. I'm then taking an Or8Way between the first 8 bits of out, another one between the last 8 bits of out, and feeding each of those outs into a Or. I'm pretty sure this is what I'm supposed to be doing. I've checked my code for bugs over and over again, but I just can't see what the problem is.

It sounds like you only have one small problem remaining. Consider what the result when you Or all the bits of a number, say x=3, together.

Also, when the ALU.tst fails, look at the the highlighted output line and compare it to the highlighted compare file line to see how your zr flag is wrong.

You can prove that your out is good by using the .tst and .cmp files in this post; they ignore zr and ng.

--Mark

[cweiss]

The hardware simulator does not allow connecting the output pins to part inputs so how can I test if out[15] = 1 to set ng? Or do a 16way OR on out for that matter?

[cadet1620]

cweiss wrote

The hardware simulator does not allow connecting the output pins to part inputs so how can I test if out[15] = 1 to set ng? Or do a 16way OR on out for that matter?

Read Appendix A.5.3 and study the example code in that section to see how to connect more than one wire to a part output.

Note that you need to create two 8-bit internal buses to connect to Or8Ways.

--Mark

[cweiss]

I had to re-read that several times to figure it out. ALU "Comparison ended successfully"!
Thanks!

[Rineez]

Thanks to you all for this discussion here. My ALU passed the test. This feels so awesome. 
I was also having trouble figuring out the zr pin. Got some hints from here. Then I just had to read the Appendix A more carefully.

[nand2cy]

Hi

CHIP Mux8Way16 {
// etc
    Mux4Way16(a=a, b=b, c=c, d=d, sel=sel[0..1], out=r1);
        Mux4Way16(a=e, b=f, c=g, d=h, sel=sel[0..1], out=r2);
// etc
}

CHIP ALU {
//etc
Or8Way(in=out[0..7], out=zr1);
Or8Way(in=out[8..15], out=zr2);
//etc
}

why the first doesn't give me error, but second ALU does?
thanks

[cadet1620]

You are running into two syntax difficulties with HDL.

First, you cannot connect a pin named in an OUT statement to any input. Second, you cannot use the sub-bus syntax on internal wires.

What you need to do is make the 8-bit buses you need for the Or8Ways in the same part where you connect to the ALU's out:

    Something16(..., out=out, out[0..7]= ...);

Study the example in appendix A.5.3 to see how multiple connections to bus input and output pins works.
(This will make 'ng' easier, too.)

--Mark

[Cythera]

Cadet1620 wrote in reply to Cardinal:  
<quote It sounds like you only have one small problem remaining. Consider what the result when you Or all the bits of a number, say x=3, together.
</quote>

I don't understand.  I don't have exactly the same problem; but I get the message "Notzinx has no source pin" pointing to line 61, which is the line after the final close brace. My code looks like this:

        Or (a=outLow, b=outHigh, out=outOr);
        Not (in=outOr, out=zr);

I'm completely confused  :(

[cadet1620]

Cythera wrote

I get the message "Notzinx has no source pin" pointing to line 61, which is the line after the final close brace. My code looks like this:

        Or (a=outLow, b=outHigh, out=outOr);
        Not (in=outOr, out=zr);

I'm completely confused  :(

Somewhere in your HDL is one or more connection 'someInput=Notzinx', but there is no corresponding 'someOutput=Notzinx'.

Note that pin names are case sensitive.

The line number indicates the end of the file because the simulator can not tell that there is no output connected to Notzinx until it gets to the end of the input.

--Mark

[Cythera]

Thank you!  ...  for rubbing my nose in the advisability of looking at all of the code.  I seem to have messed up the name of an output in line 3 somehow after the ALU without the flags had passed the simulator test.  But of course I didn't bother looking that far back because I "knew" that that part was just fine.  :(