Trouble with zr

[loof]

So, I was able to successfully implement the no-stat part of the ALU as well as ng (just take a look at the last bit :)). Now I'm trying to build the logic for the zr part, and this is what's confusing me.

I think I can explain this generally without the need for posting my code.

So, I've connected a couple sub-buses to the output of my Mux gate (the one that outputs out and no). Each sub-bus is run through a specific gate designed to handle 8 bits, and then the two outputs are put through one more gate (I'll call this output zr3) before I finally output zr.

I'm confused why this isn't working. Based on my output and the compare file, it looks like I need to negate zr3 before I output zr. Why is this the case?

Thanks in advance. I'm happy I've at least gotten through the meat of this exercise.

[WBahn]

Without knowing what this "specific gate" is or what the "one more gate" is, there's no way to tell whether your zr is correct or not and, if not, how it might not be correct.

Remember that zr should be a 1 if and only if all 16 bits at the output of the ALU are 0.

[loof]

Oh, right. It's 1 if the output is 0.

So, I'm passing each sub-bus through an Or8Way gate. Then I Or each of these outputs.

Since Or(0, 0) will spit out 0 (and not 1), we have to negate these. Correct? And vice versa if out does contain a 1.

If this is too revealing, I can erase this answer.

Thanks.

[WBahn]

You've got it.

I think your description can stay -- it's only a small piece of the whole and is a verbal description (and not code) on top of that.

[loof]

Perfect. Thanks again.