Unable to use sub of internal bus (Why?!)

[Michael Fehrenbach]

I'm working, specifically, on producing the zr output of the ALU.  My considered method is to OR the entire "out" (under an internal bus aliased "preout") against itself and then negate it, like this:

Or8Way(in=preout[0..7], out=ora);
Or8Way(in=preout[8..15], out=orb);
Or(a=ora, b=orb, out=notzr);
Not(in=notzr, out=zr);

The simulator doesn't like the use of the sub buses of preout ("sub bus of an internal node may not be used"). Is my syntax wrong in some way, or is my implementation just straight-up wrong?

I could just make a 16-in OR, but I want try to stick to the chips in the book.

[cadet1620]

Create the 8-bit buses you need with additional out= connections on tha part that is generating the output:
    SomePart(..., out[0..7]=preoutLow, out[8..15]=preoutHigh);
    Or8Way(in=preoutLow, out=ora);
    etc.

--Mark

[Michael Fehrenbach]

Thank you! My ALU is complete!

[Omar]

I have the same problem, and after implementing additional connections I get the error message
"out(1) and ora(16) have different bus widths".

Help?
 
    SomePart16(..., out[0..7]=preoutLow, out[8..15]=preoutHigh);
    Or8Way(in=preoutLow, out=ora);

[cadet1620]

I can't tell what your problem is from this post. If you want to email me your code I will take a look at it.

--Mark