# Understanding Clock Cycles Classic List Threaded 5 messages Open this post in threaded view
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## Understanding Clock Cycles

 I am a student working through the book as an independent study with a professor of mathematical logic. We are trying to understand the clock cycles which are at the heart of the memory gates in chapter 3. We both lack a background in computer engineering and architecture. Below is our abstract analysis of the bit gate and we would like to know whether we are correct: Note: Each clock cycle is an interval and is depicted by a box above, + indicates the tick In the first run(T=0 @ tick), where we have (Load=1 & In=1), these inputs are not considered yet and out = 0. On T=0 @ tock, out =1 because load & in = 1, T is now equal to 1. When T=1 is @ tick and Load = 1, In=0, Out = 1 (in(T-1)), but when T=1 is @ tock, then the Load=1 and In=0 of T=1 @ tick is considered and Out = 0 and T=2. When T=2 @ tick and Load=0 and In=0, Out is still the same as In(1). When T=2 is @ tock then Out is actually Out(T-1) which is Out(2) because T is now equal to 3, the beginning of the next clock cycle. Does this mean that when T is at tock, it is updated to T+1 first so that Out can equal Out(T-1) or In(T-1), before the In and Load bits are even considered? Thanks in advance, your feedback is truly appreciated, elshae
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## Re: Understanding Clock Cycles

 I highly recommend that you read Code (by Petzold), specifically the chapter on Flip Flops. Knowing how the edge-triggered flip flop works as a circuit is much better than resting on its theoretical behavior (in my opinion). Once you see how the circuit works, the whole input(t-1) vs. output thing becomes simple to grasp. These interactive circuit diagrams also help: http://www.play-hookey.com/digital/d_nand_latch.htmlI'm not sure about your plaintext description of the behavior... to me, it's really summed up by the PC specification (see the 'Function' declaration) and the digram below it, on page 51.
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## Re: Understanding Clock Cycles

 In reply to this post by elshae "... output pins stabilize to new values only at tocks...", from appendix a, suggests that the data-flip-flop(DFF) used is a latch. This means that the DFF is level-tiggered and thus the output reflects the inputs(controlled by the load signal in the case of a register) at the high level(tock) but stores during the low level(tick). By design therefore, the DFF retains data at a time that is one period ago, T-1, and makes it available at the current time T. So starting from time T(start of next tick and end of previous tock), out(T)=[ load(T-1) AND in(T-1) ]. At time +T (tick), out(+T)=out(T)=[ load(T-1) AND in(T-1) ]. During T+1(tock), out(T+1)=[ load(+T) AND in(+T) ]. Then at end of tock(+T+1), out(+T+1)=out(T+1)=out(current-time)=[ load(previous-time) AND in(previous-time) ]. Hopefully all this is correct and helpful. Petzold's Code gives an authoritative, but clear, insight to DFFs. Todun.