Unknown Variable: addressM

[Tejesh]

I am trying to test the CPU but when the test runs the hardware simulator gives the error "Unknown Variable: addressM". I am not understanding what this means, I have checked my HDL but couldn't find anything like addressM.

[ivant]

You should paste your code here.

[Tejesh]

Hi, here's the code
 (Update: I have manually tested my code using compare file, and fixed the errors, and tested again until I got everything right, but I am still getting this error when I try to test it with CPU .tst file).

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M?
        addressMM[15],    // AddressM in data memory (of M)
        pc[15];          // addressM of next instruction

    PARTS:
    // Put your code here:
//ALU
     And(a=instruction[11], b=instruction[15], out=c1);
     And(a=instruction[10], b=instruction[15], out=c2);
     And(a=instruction[9], b=instruction[15], out=c3);
     And(a=instruction[8], b=instruction[15], out=c4);
     And(a=instruction[7], b=instruction[15], out=c5);
     And(a=instruction[6], b=instruction[15], out=c6);
     ALU(x=DOut, y=M2Out, zx=c1, nx=c2, zy=c3,
      ny=c4, f=c5, no=c6, out=outM, out=ALUOutput, zr=zrOut, ng=ngOut);
   
//Mux1
    And(a=instruction[15], b=instruction[5], out=mux1Sel);
    Mux16(a=instruction, b=ALUOutput, sel=mux1Sel, out=mux1Out);
   
//A-Register
    Not(in=instruction[15], out=notIn15);
    And(a=instruction[5],b=instruction[15], out=andA);
    Or(a=andA, b=notIn15, out=Aload);
    ARegister(in=mux1Out, load=Aload, out=AOut,
        out[0]=AOut0, out[1]=AOut1, out[2]=AOut2, out[3]=AOut3, out[4]=AOut4, out[5]=AOut5,
        out[6]=AOut6,out[7]=AOut7, out[8]=AOut8, out[9]=AOut9, out[10]=AOut10,out[11]=AOut11,
        out[12]=AOut12, out[13]=AOut13,out[14]=AOut14,
        out[0]=addressMM[0], out[1]=addressMM[1], out[2]=addressMM[2], out[3]=addressMM[3],
        out[4]=addressMM[4], out[5]=addressMM[5], out[6]=addressMM[6],out[7]=addressMM[7],
        out[8]=addressMM[8], out[9]=addressMM[9], out[10]=addressMM[10],out[11]=addressMM[11],
        out[12]=addressMM[12], out[13]=addressMM[13],out[14]=addressMM[14]);
 
//Or8
        //JGT
        Not(in=zrOut, out=notZr);
        Not(in=ngOut, out=notNg);
        And(a=notZr, b=notNg, out=outGreater);
        And(a=instruction[0], b=outGreater, out=or81);

        //JEQ
        And(a=zrOut,b=instruction[1], out=or82);

        //JGE
        And(a=instruction[1], b=instruction[0], out=JGEand1);
        And(a=notZr, b=notNg, out=JGEand2);
        Or(a=JGEand2,b=zrOut, out=JGEor);
        And(a=JGEor, b=JGEand1, out=or83);

        //JLT
        And(a=ngOut,b=instruction[2], out=or84);
        //JNE
        And(a=instruction[0], b=instruction[2], out=JNEand);
        And(a=notZr, b=JNEand, out=or85);

        //JLE
        And(a=instruction[2], b=instruction[1], out=JLEand1);
        Or(a=ngOut, b=zrOut, out=JLEor);
        And(a=JLEand1, b=JLEor, out=or86);

        //JMP
        And(a=instruction[0], b=instruction[1], out=JMPand1);
        And(a=JMPand1, b=instruction[2], out=or87);

        Or8Way(in[0]=or81,in[1]=or82, in[2]=or83, in[3]=or84, in[4]=or85, in[5]=or86,in[6]=or87,in[7]=false, out=jmp);
        And(a=jmp, b=instruction[15], out=Or8);

//PC
    PC(in[0]=AOut0,in[1]=AOut1,in[2]=AOut2,in[3]=AOut3,
    in[4]=AOut4,in[5]=AOut5,in[6]=AOut6, in[7]=AOut7,
    in[8]=AOut8,in[9]=AOut9,in[10]=AOut10,in[11]=AOut11,
    in[12]=AOut12,in[13]=AOut13,in[14]=AOut14,

    load=Or8, reset=reset,inc=true, out[0]=pc[0], out[1]=pc[1],

    out[2]=pc[2],out[3]=pc[3],out[4]=pc[4],out[5]=pc[5],
    out[6]=pc[6],out[7]=pc[7],out[8]=pc[8],out[9]=pc[9],
    out[10]=pc[10],out[11]=pc[11],out[12]=pc[12],out[13]=pc[13],
    out[14]=pc[14]);

//D-Register
    And(a=instruction[15], b=instruction[4], out=Dload);
    DRegister(in=ALUOutput, load=Dload, out=DOut);

//Mux2
    Mux16(a=AOut, b=inM, sel=instruction[12], out=M2Out);

//writeM
And(a=instruction[15], b=instruction[3], out=writeM);
}

[WBahn]

Your code has a LOT of unnecessary connections, most of which go no where.

The problem is that you changed the interface definition. The IN and OUT pin names are not arbitrary -- they are used by the test scripts and so you can't go changing them. The test script uses the name "addressM", which is the name defined in the CPU.hdl file that was supplied to you. You changed it to "addressMM" and so when the test script runs, it is trying to look for the name "addressM" which is no longer defined.

[Tejesh]

Hi, thank you for looking at my code and examining it, however, I didn't understand what meant by "unnecessary connections which go nowhere", Because I used every connection I made. could you please tell me about it in a bit more detail?

[WBahn]

In looking closer, I see that you do use them, but you have a lot of unnecessary signals.

Your ARegister sends the output to a 16-bit signal Aout. But then you tie each of the fifteen lower bits to individual signals and then connect each individual signal separately to one of the PC input bits, and then you do this again for the memory address output signal.

Instead, do something like this:

out = AregOut, out[0..14] = jumpAddress, out[0..14] = addressM

Your design uses (if I counted correctly) 37 parts. The CPU can be implemented in half that. Having said that, implementation efficiency is not a goal of the course, just functionality, so if it works, it is good enough.

But most importantly, did you understand what I said about the issue with addressMM versus addressM?

[Tejesh]

Yes, I understood and the error message is gone now, and thank you for the example. Till now I didn't know that I could directly assign a group of bits(out[0..14]=out) to a connection like that, now that I know it does save me a lot of time and frustration.