Verilog implementation and trouble with CPU.tst

[AriaK]

I'm working on implementing the Hack platform onto an FPGA (will be using a Terasic Altera based DE1 later). I've picked up some of the basics of Verilog and implemented most of the CPU and running through tests in Icarus Verilog. I do run into an issue with CPU.tst that indicates a timing issue when setting D on the positive clock:

Here's the output with diff of CPU.cmp vs my iverilog output:

< |1+  |     0|1110110000010000|  0  |*******|   0   |12345|    1|  12345 |
---
> |1+  |     0|1110110000010000|  0  |*******|   0   |12345|    1|      0 |
15c15
< |3+  |     0|1110000111010000|  0  |*******|   0   |23456|    3|  11111 |
---
> |3+  |     0|1110000111010000|  0  |*******|   0   |23456|    3|  12345 |
31c31
< |7+  |     0|1110001110011000|  0  |  11110|   1   | 1001|    7|  11110 |
---
> |7+  |     0|1110001110011000|  0  |  11110|   1   | 1001|    7|  11111 |
39c39
< |9+  | 11111|1111010011010000|  0  |*******|   0   | 1000|    9|     -1 |
---
> |9+  | 11111|1111010011010000|  0  |*******|   0   | 1000|    9|  11110 |
75c75
< |18+ | 11111|1110000010010000|  0  |*******|   0   |    2|   22|      1 |
---
> |18+ | 11111|1110000010010000|  0  |*******|   0   |    2|   22|     -1 |
83c83
< |20+ | 11111|1110111010010000|  0  |*******|   0   | 1000|   24|     -1 |
---
> |20+ | 11111|1110111010010000|  0  |*******|   0   | 1000|   24|      1 |
115c115
< |28+ | 11111|1110101010010000|  0  |*******|   0   | 1000| 1000|      0 |
---
> |28+ | 11111|1110101010010000|  0  |*******|   0   | 1000| 1000|     -1 |
147c147
< |36+ | 11111|1110111111010000|  0  |*******|   0   | 1000| 1000|      1 |
---
> |36+ | 11111|1110111111010000|  0  |*******|   0   | 1000| 1000|      0 |

After the positive clock everything matches up. I can also validate against cpu-external, computer-add, computer-max, and computer-rect. Most of Memory.tst matches with the exception of instructions pulling the keyboard values as I haven't implemented a keyboard interface on Icarus.

Is anyone able to give some hints or know if this behavior would be expected?

Also, I'd be up for sharing notes with anyone playing around with this stuff as well.
I've had a lot of fun from these classes and am certainly looking forward to additional material!

[cadet1620]

Since all the other tests are verifying, don't worry about the mismatch with CPU.tst.

The built-in DRegister part is implemented (sort of) as master-slave part. At time T+ its test interface is showing the input value that was latched on the inactive clock edge and will appear on the output at the next active clock edge. Very confusing.

(The built-in ARegister works the same way, but it's test interface isn't used in CPU.tst.)

Here are two other changes that you may want to make to your Verilog implementation.

Question-regarding-PC-and-ARegister
Error-in-proposed-CPU-implementation

--Mark

[AriaK]

Thanks Mark. The mention of AM=A+1 in the second link sounds like it might be related to an issue I've seen in my implementation at MD=M+1 while testing Rect.hack that I didn't see if I used D=M+1 M=D (Just M=M+1 would trigger it). I'll have to look into it a bit more.

[cadet1620]

AriaK wrote

... an issue I've seen in my implementation at MD=M+1 while testing Rect.hack that I didn't see if I used D=M+1 M=D (Just M=M+1 would trigger it).

[Assuming that your CPU is all positive edge triggered.]

Depending on the RAM implementation, it may not like reading while its write enable is true. You may need to add a Memory Read register that triggers on the negative clock edge, and delay the RAM write enable until after the negative clock edge.

--Mark