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Is this something known or am I doing something wrong?
This code fails the test, address 7 takes one extra clock cycle to show up on the output, all the other addresses work as expected
CHIP RAM8 {
IN in[16], load, address[3];
OUT out[16];
PARTS:
//// Replace this comment with your code.
Mux8Way16(a=Reg0,b=Reg1,c=Reg2,d=Reg3,e=Reg4,f=Reg5,g=Reg6,h=Reg7,sel=address,out=out);
DMux8Way(in=load,sel=address,a=Load0,b=Load1,c=Load2,d=Load3,e=Load4,f=Load5,g=Load6,h=Load7);
Register(in=in,load=Load0,out=Reg0);
Register(in=in,load=Load1,out=Reg1);
Register(in=in,load=Load2,out=Reg2);
Register(in=in,load=Load3,out=Reg3);
Register(in=in,load=Load4,out=Reg4);
Register(in=in,load=Load5,out=Reg5);
Register(in=in,load=Load6,out=Reg6);
Register(in=in,load=Load7,out=Reg7);
}
Now it seems to be the last register mentionned that has the issue, if I move register at the top of the list then Reg6 has a problem. If I move all the Register statements before the DMux8Way, then it works as expected...
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Locked
