Why won't my CPU.hdl load?

[riverfish]

No idea why my CPU isn't loading into the hardware simulator. I've probably triple, quadruple and quintipled checked it already...

PARTS:
   (deleted)

[cadet1620]

[D:/TECS/projects/student/05]
% HardwareSimulator CPU.tst
In HDL file D:\TECS\projects\student\05\CPU.hdl, Line 80, b(16) and pos(1) have different bus widths: load CPU.hdl
[D:/TECS/projects/student/05]

    Mux8Way16(a=false, b=pos, c=zr, d=notng, e=ng, f=notzr, g=notpos, h=true, sel[0]=instruction[0], sel[1]=instruction[1
    ], sel[2]=instruction[2], out=prePCload);

The problem is that Mux8Way16 wants 16-bit data for a-h and out. You can change them all to a[0],...,out[0] which will make it happily ignore the other 15 bits, or make a 1-bit Mux8Way chip.

It also doesn't like [1<newline>] in that same line, but that just may be a line wrap added by my browser.

Good News! -- fix that line and your CPU passes.

I made both Mux4Way and Mux8Way because I have used multiplexors in lots of designs over the years and missed having them.


Please edit your post to remove the working HDL.

--Mark

[riverfish]

Nvm I finally got it working. Thanks cadet, once again!

On a side note - how come I never see a 'status' bar that displays an error message whenever I fail to load a chip? I'm running the simulator on a mac

[cadet1620]

% HardwareSimulator CPU.tst
In HDL file D:\TECS\projects\student\05\CPU.hdl, Line 102, b(1) and prePCload(16) have different bus widths: load CPU.hdl

   Mux8Way16(..., out=prePCload);

makes a 16-bit prePCLoad so

    PC(in=outA, load=PCload,

gets a bus width error. You need to connect only bit 0 to prePCload.


Re: not seeing the status line. On some systems it ends up off the bottom of the screen. I'm not a Mac guy. Check this form post.