Zr and Ng - ALU

[DrZoo]

I'm a bit confused on the Zr/Ng part of the ALU. I was able to construct the part with all 6 Mux16's, based on what I was told in class and what I read on other posts. I think I have the zx, nx,...,no inputs figured out. If someone would like to see that, I can email it or something.

Based on what I saw from another post, it seems like you take the output f(x,y). If it is zero, zr = 1, otherwise it is 0. And if output f(x,y) < 0, then ng = 1, otherwise it's 0.

The only thing the book says about zr and ng is this:
if out=0 then zr = 1 else zr = 0 // 16-bit eq. comparison
if out<0 then ng = 1 else ng = 0 // 16-bit neg. comparison

I'm not exactly sure where to go from here. The last thing I have done is negating the output. After that, I feel lost.

// Negate the output
    Not16(in=xyOut, out=xyNot);
    Mux16(a=xyOut, b=xyNot, sel=no, out=out);

// Zr/Ng

[cadet1620]

DrZoo wrote

I'm a bit confused on the Zr/Ng part of the ALU.
...

I'm not exactly sure where to go from here. The last thing I have done is negating the output. After that, I feel lost.

// Negate the output
    Not16(in=xyOut, out=xyNot);
    Mux16(a=xyOut, b=xyNot, sel=no, out=out);

// Zr/Ng

First, make sure that your ALU is passing ALU-nostat.tst. If it does, then the computation portion of your ALU is good.

For the 'ng' output, think about 2's-complement numbers. What bit indicates that a number is negative? You can connect that bit to 'ng' in the final Mux16 in your ALU by adding a sub-bus connection to the Mux16's 'out'.

For the 'zr' output, you need to detect when 'out' == 0. In this case all 16 of 'out's bits are 0. If any of the bits are 1, then 'out' != 0. You made a part that can detect if any one of its 8 inputs is 1. You will want to use two of them and a couple other parts to generate 'zr'. This will require two more sub-bus connections to the Mux16's 'out'.

--Mark

[DrZoo]

I did not know that ALU-nostat.tst was a thing! My ALU did indeed pass that part successfully. Thanks for your explanation. I'll give it a shot and post back if I have any questions.

To answer the two's complement question it would be the last bit out[15], right?

Thanks!

[DrZoo]

I think I understood the sub buses for the Mux by doing this Mux16(a=xyOut, b=xyNotOut, sel=no, out=out, out[15]=ng, out[0..7]=zr1, out[8..15]=zr2);

Now to compare zr1 and zr2 I'll need 2 Or8Way() to see if any of the 8 inputs are a 1. Then Or both of those together, right?

[Vijay99]

Mux16(a=f1, b=notf1, sel=no, out=out);
Or16Way(in=out, out=zr1);

The above code was repeatedly giving the error: "cannot connect the output to part."
I wonder where I could have found the instructions to code relevant outputs within Mux16(a=xyOut, b=xyNotOut, sel=no, out=out, out[15]=ng, out[0..7]=zr1, out[8..15]=zr2)

[WBahn]

Vijay99 wrote

Mux16(a=f1, b=notf1, sel=no, out=out);
Or16Way(in=out, out=zr1);

It's hard to tell what might be wrong since we have no idea about the signals you are using. Furthermore, you are using a part that is not part of the list of parts you are expected to build, so there's no test script for it. How well did you test it?

The above code was repeatedly giving the error: "cannot connect the output to part."
I wonder where I could have found the instructions to code relevant outputs within Mux16(a=xyOut, b=xyNotOut, sel=no, out=out, out[15]=ng, out[0..7]=zr1, out[8..15]=zr2)

There are a few places to find this information. The best is perhaps the Hardware Construction Survival Kit that is linked at the top of the forums for the early chapters. It is also hinted at in Appendix A of the text, though not very well.