different bus widths

[afsd]

Not(in=zx, out=notzx);
And16(a=x, b[0..15]=notzx, out=x1);

why doesn't this work?

[cadet1620]

afsd wrote

Not(in=zx, out=notzx);
And16(a=x, b[0..15]=notzx, out=x1);

why doesn't this work?

The problem is that b[0..15] is a 16-bit bus (same as b by itself) and notzx is a single wire.

I originally built my ALU this way by making a chip called Widen16 with 1-bit in and 16-bit out that I could use to make code basically identical to yours work:
    Not(in=zx, out=notzx);
    Widen16(in=notzx, out=notzx16)
    And16(a=x, b=notzx16, out=x1);

With a bit more thought, I realized that I could make the ALU using only the TECS chips by choosing what values get presented to the And/Add rather than computing them.

Note that the built-in constants true and false will match any bus width.

--Mark

[afsd]

an example in the book seems to allow attaching an internal pin to multiple with that syntax

Foo(in[2..4]=v, in[6..7]=true, out[0..3]=x, out[2..6]=y)

I used a mux instead to get the ALU working but still curious as to why that doesn't work

[afsd]

oh nvm I misread, "v" is actually 3 bits, etc


Thanks