direction of connections (assignments) in HDL

[Marc Antzis]

Direction of connections (assignments) in HDL
I am working my way through the chapter 1 assignments and I am trying to figure out
the direction of the connections (assignment) of the passed inputs and outputs
Here is my working and tested And example:
CHIP And{
        IN a, b;
        OUT out;
        PARTS:
                SomePart(..., out=out1);
                AnotherPart(in=out1, ...);
}

are the inputs right to left or left to right?
What about the outputs?
The reason I ask is "out1" is on the same side of the equal sign

thanks

[Edited by admin to remove And solution.]

[cadet1620]

HDL is connecting wires together, not assigning variable values. This is an important distinction.

The signal name on the left of the '=' is a signal (I/O pin) in the part being used; the name on the right is a signal (I/O pin or internal wire) in the part being designed.

Read the Hardware Construction Survival Kit and Helpful HDL Philosophy.

[Forum etiquette is not to post complete solutions. Please edit your post to remove the correct solution to And.]

--Mark

[marc antzis]

thanks for the help

i apologize. i did not realize
can you delete post i dont know how to edit post

[cadet1620]

I edited it for you. If you become a registered forum member you can edit your own posts. It's an option under the More button.

--Mark