Re: fetch-execute cycle, instruction input, and Mux16 sel bit
This post was updated on .
The Mux16 spec says if sel=0 then a, else b.
Therefore the CPU implementation looks backward.
Maybe the "a" and "b" inputs on the Mux16 have nothing to do with top-bottom, up-down?
This is exactly the case. The diagram is just saying that you need to somehow choose between these two signals. The details of which signal goes to port a and which go to port b are left up to you.
Also, note that they don't say that you have to drive the select input with the msb of the instruction. You are choosing to do that (and it is a perfectly reasonable choice). You could have decided, for whatever reason, to go through a Not gate on the msb so that is was an A-type instruction when that signal was HI. Since the diagram doesn't define the signal to be used for the control input to the mux, it isn't in a position to dictate which data signal goes to which input port.