fetch-execute cycle, instruction input, and Mux16 sel bit

[ouverson]

I wanted to make sure I was tracking with the fetch-execute cycle.

Slide 35: https://docs.wixstatic.com/ugd/56440f_96cbb9c6b8b84760a04c369453b62908.pdf

In the proposed partial implementation of the CPU, the instruction input is fed into one of the Mux16 inputs (the "b" input); ALU output is fed into the other Mux16 input (the "a" input).

It looks as if the "a" input should come from instruction and the "b" input should come from the ALU output - opposite of what is shown.

My reasoning:

I have the Mux16 sel bit coming from instruction[15].

When an A-instruction is coming in instruction[15]=0; and I want the value stored in the A register to come from the instruction.

When a C-instruction is coming in instruction[15]=1; and I want the value stored in the A register to come from ALU output.

The Mux16 spec says if sel=0 then a, else b.

Therefore the CPU implementation looks backward.

Maybe the "a" and "b" inputs on the Mux16 have nothing to do with top-bottom, up-down?

[WBahn]

ouverson wrote

The Mux16 spec says if sel=0 then a, else b.

Therefore the CPU implementation looks backward.

Maybe the "a" and "b" inputs on the Mux16 have nothing to do with top-bottom, up-down?

This is exactly the case. The diagram is just saying that you need to somehow choose between these two signals. The details of which signal goes to port a and which go to port b are left up to you.

Also, note that they don't say that you have to drive the select input with the msb of the instruction. You are choosing to do that (and it is a perfectly reasonable choice). You could have decided, for whatever reason, to go through a Not gate on the msb so that is was an A-type instruction when that signal was HI. Since the diagram doesn't define the signal to be used for the control input to the mux, it isn't in a position to dictate which data signal goes to which input port.

[ouverson]

Yes, I see that I will need to add some additional logic in order to solve the control bus implementation.

It is really making me think about the orchestration of the fetch-execute cycle, the machine language specification, and the hardware components.

I now have a greater appreciation for why the course creators needed to cover Machine Language prior to constructing the Hack Computer.

I find this hardware, machine language interfaces fascinating; so much history.