# hdl code for bus

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## hdl code for bus

 Can someone point me to some good explanation on how to define the parts of a chip when buses are involved? I am already struggling with the and16 implementation because I cannot work out how to name the different connections. Thank you!
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## Re: hdl code for bus

 Administrator Look at the HDL Survival Guide http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/Hardware-Construction-Survival-Kit-tp3385741.htmlBusing is addressed toward the bottom. I agree that subbusing is not very intuitive in this HDL. If you still have questions, we can go from there.
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## Re: hdl code for bus

 Thanks for the reply. Unfortunately, I do not understand sufficiently the description in the survival guide in this case. I tried all possible combinations of how to describe the three parts of the and16, but none of them worked. Is there any location that describes in detail how to define parts when inputs and outputs are a multi-bit bus? For example, one of my tries looks like this: Nand(a=a[16], b=b[16], out=Nand1); Nand(a=a[16], b=b[16], out=Nand2); Nand(a=Nand1, b=Nand2, out=out[16]); So I call the connections between the Nand parts Nand1 and Nand2. And somewhere I read that the number of bits for an internal pin are implicitly derived from the input that they are connected to, i.e in this case the a[16] and b[16]. Can you please give a hint how this needs to be written instead? Thanks Dom
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## Re: hdl code for bus

 Administrator For some of the gates basic gates, the width of the gate is implied. But you have to be consistent. You are trying to great a 16-bit NAND gate that has sixteen inputs for 'a' and 'b', but only a single output. I would recommend not using the implied-width feature of the basic gates. It's really there to reduce the number of Java part modules that have to be written. In your example, you have a some single signal wires, namely a[16], b[16], Nand1, Nand2, and out[16]. NONE of these are buses, through three of them are part of larger buses. A bus is indicated by a signal name such as a[0..15]. This is a sixteen bit bus. If you want the lower four bits, it would be a[0..3]. If you want just the msb, it would be a[15].
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## Re: hdl code for bus

 Thanks. Then why are the chip inputs and output in the and16 file that we received described as CHIP And16 {     IN a[16], b[16];     OUT out[16]; You are writing that [16] means single signal. Why does it in this case work to describe a bus? Based on your comments I tried the following to describe the parts but still fail on the first line: Nand(a=a[0..15], b=b[0..15], out=Nand1[0..15]); Nand(a=a[0..15], b=b[0..15], out=Nand2[0..15]); Nand(a=Nand1[0..15], b=Nand2[0..15], out=out[0..15]); Any more hint that you can give? Thanks!