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Can someone point me to some good explanation on how to define the parts of a chip when buses are involved? I am already struggling with the and16 implementation because I cannot work out how to name the different connections.
Thank you!
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Thanks for the reply. Unfortunately, I do not understand sufficiently the description in the survival guide in this case. I tried all possible combinations of how to describe the three parts of the and16, but none of them worked. Is there any location that describes in detail how to define parts when inputs and outputs are a multi-bit bus?
For example, one of my tries looks like this:
Nand(a=a[16], b=b[16], out=Nand1);
Nand(a=a[16], b=b[16], out=Nand2);
Nand(a=Nand1, b=Nand2, out=out[16]);
So I call the connections between the Nand parts Nand1 and Nand2. And somewhere I read that the number of bits for an internal pin are implicitly derived from the input that they are connected to, i.e in this case the a[16] and b[16].
Can you please give a hint how this needs to be written instead?
Thanks
Dom
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Administrator
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For some of the gates basic gates, the width of the gate is implied. But you have to be consistent. You are trying to great a 16-bit NAND gate that has sixteen inputs for 'a' and 'b', but only a single output.
I would recommend not using the implied-width feature of the basic gates. It's really there to reduce the number of Java part modules that have to be written.
In your example, you have a some single signal wires, namely a[16], b[16], Nand1, Nand2, and out[16]. NONE of these are buses, through three of them are part of larger buses.
A bus is indicated by a signal name such as a[0..15]. This is a sixteen bit bus. If you want the lower four bits, it would be a[0..3]. If you want just the msb, it would be a[15].
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Thanks. Then why are the chip inputs and output in the and16 file that we received described as
CHIP And16 {
IN a[16], b[16];
OUT out[16];
You are writing that [16] means single signal. Why does it in this case work to describe a bus?
Based on your comments I tried the following to describe the parts but still fail on the first line:
Nand(a=a[0..15], b=b[0..15], out=Nand1[0..15]);
Nand(a=a[0..15], b=b[0..15], out=Nand2[0..15]);
Nand(a=Nand1[0..15], b=Nand2[0..15], out=out[0..15]);
Any more hint that you can give? Thanks!
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Administrator
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Fair question.
The IN / OUT statements are port declarations and they need to only know the width of input and output ports, while what we were discussing earlier were the HDL statements where the statements were being used as signals
and so what was important there is WHICH of the signals within the bus are being used.
It's like when you declare an array in C (or most languages) versus when you actually use it.
From: djbell [via Nand2Tetris Questions and Answers Forum] <ml+[hidden email]>
Sent: Sunday, May 26, 2019 9:02:53 AM
To: William Bahn
Subject: Re: hdl code for bus
Thanks. Then why are the chip inputs and output in the and16 file that we received described as
CHIP And16 {
IN a[16], b[16];
OUT out[16];
You are writing that [16] means single signal. Why does it in this case work to describe a bus?
Based on your comments I tried the following to describe the parts but still fail on the first line:
Nand(a=a[0..15], b=b[0..15], out=Nand1[0..15]);
Nand(a=a[0..15], b=b[0..15], out=Nand2[0..15]);
Nand(a=Nand1[0..15], b=Nand2[0..15], out=out[0..15]);
Any more hint that you can give? Thanks!
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Thanks for the explanation. This is clear now.
Can you then please give a hint why the first part description does not work? In my understanding there is a 16 bus on all connections throughout the chip. Just like 16 separate And's
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