how RAM64+ unit can read/write independant registers ?

[trogne]

I don't understand how RAM64+ unit can read/write independant registers.

The "RAM8.hdl" can write to 8 different registers. This I understand.

But above that it's simply defer to lower levels, until reaching RAM8 and always read/write to the same 8 RAM8 registers.

For example, "RAM64.hdl" :  

It takes "address[6]", but then defer to RAM8 :  RAM8(in=in, load=l1, address=address[0..2], out=t1);

And there it will read/write to only the 8 basic registers.

So, how can the RAM64 address be independant ?

To me, read/write only occurs on the last 3 bits.

So, 010110 have the same value than 101110 , or any xxx110 ...

I guess I'm missing something !

[cadet1620]

The RAM16 contains 8 RAM8s. Each one of those RAM8 contains 8 Registers, so there are a total of 64 Registers.

The structure of the RAM64 is the same as that of the RAM8, except that the Registers in the RAM8 are replaced by RAM8s in the RAM64.  Three of the RAM64's address bits control which RAM8 is active -- its output is sent the the main 'out' and it gets loaded if the main 'load' input is true -- and the other 3 address bits are connected the RAM8s.

For addr = 010011, all RAM8s read word 3, and logic in the RAM64 selects RAM8 #2's 'out' for the main 'out' output.
If the main 'load' input is true then logic in the RAM64 ensures that only RAM8 #2's 'load' is true, and the other RAM8's will be unaffected.

--Mark

[trogne]

"Three of the RAM64's address bits control which RAM8 is active -- its output is sent the the main 'out' and it gets loaded if the main 'load' input is true -- and the other 3 address bits are connected the RAM8s."

But if load is false, that means I want to read. So all RAM8 is selected with load 0.
Then all the RAM8 are the same ?  Cause same 3 bit address ?


"For addr = 010011, all RAM8s read word 3, and logic in the RAM64 selects RAM8 #2's 'out' for the main 'out' output.
If the main 'load' input is true then logic in the RAM64 ensures that only RAM8 #2's 'load' is true, and the other RAM8's will be unaffected. "

Only RAM8 does the "register with dff" (Register.hdl then Bit.hdl).
How can RAM64 registers be independant if they do not the "register with dff" ?

What I see is that all RAM8 are selected with the same address!

Then RAM64 selects one of them.

So value at all address xxx010 are the same.

I'm totally lost.

[ivant]

trogne wrote

What I see is that all RAM8 are selected with the same address!

Then RAM64 selects one of them.

So value at all address xxx010 are the same.

It's like having 8 towns with exactly the same street names in them. If you only use the street name and number, you'll select 8 different houses. It doesn't mean that the same people live in each of them though, right?

Each house is in different town, so the town name (or its postal code) can be used to choose exactly one of them.

[trogne]

Thanks for the analogy. I like that.

What confuse me most is that, for RAM64, the 3 most significant bits, never reach the bits process in Bit.hdl :

CHIP Bit {
    IN in, load;
    OUT out;

    PARTS:
    Mux(a=t1, b=in, sel=load, out=w1);
    DFF(in=w1, out=t1, out=out);
}


In RAM64 there's 8 lines like that :
RAM8(in=in, load=l1, address=address[0..2], out=t1);


That makes 64 registers, and I understand that.  But the fact that only the [0..2] part of the address finally reach the Bit.hdl process is confusing me.
For example, how the value at address 010101 can be remembered, if ONLY the last part, 101, reaches the Bit.hdl process ?


Is this why it's called "Register.hdl" instead of "RAM.hdl" ?

[cadet1620]

Why don't the parts inside the RAMs need to know all the address bits?

A spy agency wants a pizza delivered, but they are so paranoid that they don't want anyone to know any more than they need to get the pizza to the right office on the right floor in the right building...

Pizza guy gets an envelope with a building address on it, and takes the pizza there and gives it and the envelope to the doorman.

The doorman opens the envelope and inside is another envelope with the floor number written on it. He gives the pizza and the new envelope to the elevator operator, who takes them to the security guard on the designated floor.

The security guard opens the envelope, gets the room number, and takes the pizza down the hall.

In each step of this pizza delivery, some bits of the address are discarded (in a good spy thriller, the operatives probably eat the envelopes after they open them).

--Mark

[trogne]

Another great analogy :)

I think I understand now.

So, for RAM64, with 010101 and 110101, the last part is the same (101), but it's not the same wires !! Right ?

010101 makes all it's way down to single 1-bit registers pertaining to 101, but it's the 101 wires of 010.

110101 makes all it's way down to single 1-bit registers pertaining to 101, but it's the 101 wires of 110.


And we devide the six bits in 2, like we do in real-life, with a matrix of 8x8 latches. Once a column or row is selected, we then work on the remaining 8 columns/rows.

[ivant]

cadet1620 wrote

(in a good spy thriller, the operatives probably eat the envelopes after they open them).

In a parody, they would eat the pizza and deliver the envelopes! At least that's what would do given the two choices :)

[ivant]

trogne wrote

Another great analogy :)

I think I understand now.

So, for RAM64, with 010101 and 110101, the last part is the same (101), but it's not the same wires !! Right ?

010101 makes all it's way down to single 1-bit registers pertaining to 101, but it's the 101 wires of 010.

110101 makes all it's way down to single 1-bit registers pertaining to 101, but it's the 101 wires of 110.

Basically yes, except I'm not sure what you mean by the "but it's not the same wires" part.

trogne wrote

And we devide the six bits in 2, like we do in real-life, with a matrix of 8x8 latches. Once a column or row is selected, we then work on the remaining 8 columns/rows.

The term divide is a bit overloaded. Do you mean splitting the bits or a mathematical division?

[trogne]

By "not the same wires", I mean that "101" is not using the same gates in 111101 and 000101.
So that 111101 is physically "stored" somewhere, and 000101 somewhere else.

The "101" in RAM64 111101 and 000101 are two separate sets of gates. It's just that both "101" act the same way.


Yes, divide is not the right term. I meant splitting, like 111 for the column, 101 for the row.

[cadet1620]

Yes, you understand correctly.  It is too easy at first to think that the parts are subroutine calls, and many students get confused with the Bit because they are thinking about the execution order of subroutine calls.

Think about this: It would be an awful lot of typing, but you could construct DMux64Way and Mux64Way16 inline in RAM64 using cascaded mux and demux parts, and use 64 Registers, and it would be the logically identical part as your RAM64 using RAM8Way!

[Excelent, Ivan! I'm envisioning it as a Monty Python skit with the last scene being the floor guard slipping the envelope under the door and walking back down the hall eating the last piece!]

--Mark