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This post was updated on .
I'm working on my CPU implementation: the jump control bits specifically.
The jump control looks like it will need a truckload of And, Or and Not gates. In order to reduce the number I can, of course, use an Or8Way, and wire a Not gate to each jump instruction and fan out accordingly, but it still seems like a lot of And'ing and Or'ing.
Here's what I've got thus far:
C-instruction opcode / instruction[15] = a
Jump bit 3 / instruction[0] = b
Jump bit 2 / instruction[1] = c
Jump bit 1 / instruction[2] = d
zr out of ALU = e
ng out of ALU = f
THese are the scenarios where I need load = 1
a b c d e f
1 0 0 1 0 0
1 0 1 0 0 1
1 0 1 1 0 1
1 0 1 1 0 0
1 1 0 0 1 0
1 1 0 1 1 0
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 0 0 1
1 1 1 1
I see that I can pull the C-instruction opcode to end of And, Or gates to a final And gate: instruction[15] And ... Or, Or, Or, etc.
In previous projects, it was easier for me to see a pattern to reduce the gates (though the PC did take me some hours and help from the community).
Maybe there is no easy way to implement the jump control other than wiring together Not, And and Or gates; but figured I asked.
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