project 5- CPU

[meir]

hi,
I don't understand why the simulator can't even load my program,
help me please..

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M?
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    // Put your code here:
        Mux16(a=instruction, b=outalu ,sel=instruction[15] ,out=aorc);
        Not(in=instruction[15] ,out=typea);
        Or(a=typea ,b=instruction[5] ,out=loada);
        ARegister(in=aorc ,load=loada ,out=addressM, out=outa);
        DRegister(in=outalu ,load=instruction[4] ,out=outd);
        Mux16(a=outa ,b=inM ,sel=instruction[11] ,out=aorm);
        ALU(x=outd ,y=aorm ,zx=instruction[11] ,nx=instruction[10] ,zy=instruction[9] ,ny=instruction[8] ,f=instruction[7] ,no=instruction[6] ,out=outalu, out=outM ,zr=eq ,ng=ld);
        And(a=instruction[15] ,b=instruction[3] ,out=writeM);
       
        PC(in=outa ,load=g ,inc=True ,reset=reset ,out= pc);
       
        Or(a=ld ,b=eq ,out=or0);
        Not(in=or0 ,out=or1);
        Or(a=instruction[1] ,b=instruction[2] ,out=m1);
        Not(in=m1 ,out=m2);
        And(a=or1 ,b=m2 ,out=m3);
        And(a=m3 ,b=instruction[0] ,out=m!);
       

        And(a=instruction[1] ,b=eq ,out=e1);
        Or(a=instruction[0] ,b=instruction[2] ,out=e2);
        Not(in=e2 ,out=e3);
        And(a=e3 ,b=e1 ,out=e!);
       
        Or(a=e! ,b=m!,out=i!);
       
        Or(a=instruction[0] ,b=instruction[1] ,out=r1);
        Not(in=r1 ,out=r2);
        And(a=ld ,b=instruction[2] ,out=r3 );
        And(a=r3 ,b=r2 ,out=r!);
       
        And(a=instruction[0] ,b=instruction[2] ,out=s1 );
        Or(a=instruction[1] ,b=eq ,out=s2);
        Not(in=s2 ,out=s3);
        And(a=s3 ,b=s1 ,out=s!);
       
        Or(a=r! ,b=e!,out=o!);
       
        And(a=instruction[0] ,b=instruction[1] ,out=n1);
        And(a=n1 ,b=instruction[2], out=n!);
       
        Or(a=m! ,b=e! ,out=more );
        Or(a=i! ,b=r! ,out=iorr );
        Or(a=s! ,b=o! ,out=soro );
        Or(a=n! ,b=more ,out=normore);
        Or(a=iorr ,b=soro ,out=iorrorsoro);
        Or(a=normore ,b=iorrorsoro ,out=orsum);
        And(a=orsum ,b=instruction[15] ,out=g);
}

[WBahn]

The simulator should give you some kind of error message down at the bottom. What does it say?

In looking over your code briefly, I see that one problem you have is that some of your bus connects don't have consistent widths.

For instance, addressM is a 15-bit bus. You can't connect that signal directly to the output of a part that produces a 16-bit bus.

I also see several illegal signal names. Go back and review what the rules are for signal names in the hardware simulator.

[meir]

thank you for your time.
i fixed the problem with the consistent width, and mor mistakes that i found,
now it's work!!

PARTS:
    // Put your code here:
        Mux16(a=instruction, b=outalu ,sel=instruction[15] ,out=aorc);
        Not(in=instruction[15] ,out=typea);
        Or(a=typea ,b=instruction[5] ,out=loada);
        ARegister(in=aorc ,load=loada ,out[0..14]=addressM, out=outa);
        DRegister(in=outalu ,load=instruction[4] ,out=outd);
        Mux16(a=outa ,b=inM ,sel=instruction[12] ,out=aorm);
        ALU(x=outd ,y=aorm ,zx=instruction[11] ,nx=instruction[10] ,zy=instruction[9] ,ny=instruction[8] ,f=instruction[7] ,no=instruction[6] ,out=outalu, out=outM ,zr=eq ,ng=ld);
        And(a=instruction[15] ,b=instruction[3] ,out=writeM);
       
        PC(in=outa ,load=g ,inc=true ,reset=reset ,out[0..14]= pc, out[15]=just);
       
        Or(a=ld ,b=eq ,out=or0);
        Not(in=or0 ,out=or1);
        Or(a=instruction[1] ,b=instruction[2] ,out=m1);
        Not(in=m1 ,out=m2);
        And(a=or1 ,b=m2 ,out=m3);
        And(a=m3 ,b=instruction[0] ,out=mf);
       

        And(a=instruction[1] ,b=eq ,out=e1);
        Or(a=instruction[0] ,b=instruction[2] ,out=e2);
        Not(in=e2 ,out=e3);
        And(a=e3 ,b=e1 ,out=ef);
       
        Or(a=or1 ,b=eq ,out=iw);
        And(a=instruction[0] ,b=instruction[1] ,out=ik );
        And(a=ik ,b=iw ,out=if);
       
       
        Or(a=instruction[0] ,b=instruction[1] ,out=r1);
        Not(in=r1 ,out=r2);
        And(a=ld ,b=instruction[2] ,out=r3 );
        And(a=r3 ,b=r2 ,out=rf);
       
        And(a=instruction[0] ,b=instruction[2] ,out=s1 );
        Or(a=instruction[1] ,b=eq ,out=s2);
        Not(in=s2 ,out=s3);
        And(a=s3 ,b=s1 ,out=sf);
       
        Or(a=ld ,b=eq ,out=yf);
        And(a=yf ,b=n1 ,out=kf);

       
       
        And(a=instruction[2] ,b=instruction[1] ,out=n1);
        And(a=n1 ,b=instruction[0], out=nf);
       
        Or(a=mf ,b=ef ,out=more );
        Or(a=if ,b=rf ,out=iorr );
        Or(a=sf ,b=kf ,out=soro );
        Or(a=nf ,b=more ,out=normore);
        Or(a=iorr ,b=soro ,out=iorrorsoro);
        Or(a=normore ,b=iorrorsoro ,out=orsum);
        And(a=orsum ,b=instruction[15] ,out=g);
}