HDL implementation of Bit gate

Posted by rick2047 on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/HDL-implementation-of-Bit-gate-tp1392879.html

Hey,
I am trying to implement the HDL code for the bit gate. I am using the implementation in fig 3.1 as a reference. But I cannot get it to work. Actually I cannot understand how to clock the chips where does the CLOCKED keyword comes. this is what I have wrote so far



CHIP Bit {



    IN  in, load;

    OUT out;

   
    PARTS:
   

    Mux(a=in,b=out,sel=load,out=muxout);
    DFF(in=muxout,out=out);

}


but of course I cannot connect out to the input of Mux. How do I go about doing it.