Re: HDL implementation of Bit gate

Posted by rick2047 on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/HDL-implementation-of-Bit-gate-tp1392879p1395377.html

I need to put the output of DFF into the mux that is clear. But I cannot possibly do that, then I need either a buffer or some fancy And-ing with true thing. But And-ing would be just HDL getting in my way. How do I do that. I hate it when the HDL comes into my way. Also I do not understand why I cannot just connect out to the input b of Mux. If I can do it in hardware (and it would work due to the clocked property of DFF) why not in the HDL. The HDL is supposed to reflect the hardware.