HDL does not appear to conform to specification in Appendix A

Posted by jsp1611 on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/HDL-does-not-appear-to-conform-to-specification-in-Appendix-A-tp3308829.html

Hi there,
I've been playing around with HDL whilst working through chapter 3. I've reread appendix A a few times, and I'm a bit confused.

Appendix A appears to state that HDL supports the keywords "BUILTIN" and "CLOCKED", but I get errors in the hardware simulator whenever I try and open a file with these keywords in. For example, the following definition for Bit is not accepted by the Hardware simulator:

CHIP Bit {

    IN  in, load;
    OUT out;
    BUILTIN DFF;
    CLOCKED in, out;

    PARTS:
    Mux(a=feedback,b=in,sel=load,out=dffin);
    DFF(in=dffin,out=out,out=feedback);
}

But if I remove the lines "BUILTIN" and "CLOCKED" this chip works.

What is going on here? Are these keywords supported or not? Have I misread the text?

Jon