Re: Program Counter Implementation

Posted by Tom1984 on Mar 25, 2012; 4:47pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Program-Counter-Implementation-tp2974049p3855930.html

cadet1620 wrote

The spec says that if reset is active, load and inc are don't cares.  When load is active, inc is don't care.

Firstly, as a self-learner trying to follow TECS, I'd like to say a huge "thank you" to the creators of this forum and to the admins who are helping people like me! I'll try to ask my question without posting spoilers...

I've been trying to follow the advice in this thread, but am still completely stuck on this chip. Cadet's  comment above suggests to me that the logic of the circuit needs to be (working from in to out):

In > Increment? > Load? > Reset? > Out

I think I have written my HDL in this way, starting with a Mux16 to select either "in" or "in" passed through the Incrementer chip from Ch2, followed by a Register chip, and finally a Mux16 to select either the previous operations or 0. My comparison fails almost immediately.

Am I on anything near the right lines here please?