Re: HDL implementation of Bit gate

Posted by AntonioCS on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/HDL-implementation-of-Bit-gate-tp1392879p3856920.html

I stopped the reading of this book due to work/time issues and was now picking it up again. I couldn't make my bit implementation work.

I googled for the answer and was surprised to see that the path I was taking was almost correct (missed the or instruction).
In the illustration on page 43 we see that the DFF comes after the Mux but in hdl this will come first. I was doing so but was not really sure. I really hate it when the illustrations confuse me like this.

Hope I have better luck with the remaining chips.

Note: I haven't quite fully understood the implementation of this chip. I have reread chapter 3 a few times but I must be missing something obvious.