Re: Program Counter Implementation

Posted by Tom1984 on Mar 26, 2012; 6:48pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Program-Counter-Implementation-tp2974049p3859022.html

I'm still really struggling with this chip, and I wonder if it's because I have misunderstood the notes in the Implementation section:

Counter A w-bit counter consists of two main elements: a regular w-bit register, and combinational logic. (TECS p52)

I'm reading this as saying "the only sequential logic employed here is a single, standard, 16-bit register". But then I'm having trouble seeing how the counter can store the values set by inc and reset, when load only determines whether or not the original input is fed in.

EDIT: If load is a don't care when reset is active, how is "0" fed back into the chip to be repeated / incremented?

cadet1620 wrote

Where in this sequence should the DFF go

Do you mean there needs to be a further DFF/DFFs after the register, Mark?

Thanks
Tom