Trouble implementing memory chip

Posted by AndyGeo on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Trouble-implementing-memory-chip-tp4025962.html

It's been a while since I completed chapter 3 and the RAM chips but I went back to refresh.

Those chips were built of 4 or 8 smaller chips so a DMux 4 or 8 way worked. With the MSB xx or xxx used respectively to pinpoint the particular address.

Whats throwing me here is that this chip isn't built like those exactly.

I used a DMux and the first bit of address as sel. Up until the keyboard is needed in the test file it matches the compare file. But I'm not too sure how to use the keyboard chip and to interpret the differing addresses.