Re: Full Adder Implementation

Posted by cadet1620 on Sep 27, 2013; 2:08pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Full-Adder-Implementation-tp4027337p4027339.html

Sobbity wrote

Greetings, just recently started working on these projects and was wondering what the minimum number of gates for the more "direct" implementation of the Full-Adder would be, without the usage of Half-Adders.

Depends on what a "gate" is and what you're trying to minimize. For instance, the minimum implementation of a half adder is an Xor and an And. Using 2 of these and an Or to combine the carries would get you a 5 gate solution.

For a 2-input Nand only gate count minimization, there is a 4 Nand Xor that you can use. It has internal gates that you can use to generate the carry with just one more Nand, so that would be be 9 gates.

For speed optimization you need to know what type of IC you are designing for. Different IC families can implement logic in more efficient ways then 2-input Nand gates only.  TTL for instance can implement N-input Nand for no extra delay and very little extra silicon. It's perfect for sum of products implementations. Calling Not a 1-input Nand gate, you can build a full adder with 12 Nand gates that has only 2 gate delays for carry and 3 gate delays for sum.

For CMOS, there are many optimization tricks that involve non-traditional logic like transmission gates and bi-directional pass transistors. I've seen a 14 transistor design.

--Mark