Re: Special XOR for half-adder and full-adder

Posted by jonk on Mar 02, 2016; 7:20pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Special-XOR-for-half-adder-and-full-adder-tp4029600p4029608.html

I've used ECL only the early 1980's. They keep the BJTs out of saturation for speed. Nice.

My experience in designing CPUs is mostly where I've targeted Xilinx FPGAs (4000 series, back in the day) using VHDL. I only have very limited experience with verilog.

Carry look ahead, of some form, is usually used with adders. I understand that. Usually where some kind of balance is struck between group size, acceleration of carry, propagation delays, etc. Non-trivial, in practice. But fun.

In the case of the 9-NAND full adder, and assuming NAND as the canonical delay, the carry out takes 5 gate delays and the sum takes 6 gate delays. One less gate delay is only a small bit of luck, though. As you add stages, this gets to be pretty ornery, of course, as the carry ripples across stages.

By the way, I've not yet gotten far enough into the course. But subtraction is really quite easy without a new function code for the ALU. You can mux the Q and /Q outputs from registers to select the complement and then feed (mux) in a "1" as the carry into the ALU in order to complete the twos-complement negation and create a subtraction. Even when the ALU itself only supports addition directly. Just a matter of execution control logic, is all.

I'm really enjoying the simulator that accepts a modest HDL language. I would like to consider doing more with it -- including allowing folks to enter combinatorial and sequential logic using schematic capture, logic tables, and so on. Perhaps more. I guess I wish there were a very nice, very flexible tool that was freely available and where people can use whatever they prefer in terms of describing each aspect of their project. I'd also like it to be capable of accepting constraints and doing an excellent job of optimizing (say, a table) to a set of logic and/or selected chip specifications. That part seems the most interesting to me -- and difficult. But fun.

Thanks so much for discussing this and suggesting taking a quick look at the NOR, as well. It's been decades for me since I'd bothered much with this stuff and the interaction really helps me a lot to recover and re-think stuff I've long since forgotten now.

I'm also VERY glad to see someone, anyone really, trying to invigorate an interest in how computers work. One of the only books I know of, perhaps aside from the one recommended for this class, is "Bebob BYTES Back: An Unconventional Guide to Computers" by Clive Maxfield and Alvin Brown. That is, one that is targeted at someone completely untrained in this area.

I built my first computer at home using 7400 series gates and a HUGE amount of wire-wrap. I also designed the power supply for it. This was in 1974. It was a wonderful experience.

I'm considering the idea of developing a series of physical modules, something akin to Elenco's 750R kit of Snap Electronics. I'd like to base it on a 4-bit bus width per "connection" so that an 8-bit ALU isn't trivial and requires "some work" while at the same time not having to have an entire floor available for laying out a full CPU. I think slicing it at 4 bits might force enough learning while at the same time making a full 8-bit CPU achievable without near-infinite floor space to complete it. With the availability of micros at such cheap cost, it shouldn't have to be too expensive. I've already contacted Elenco about the possibility of having them manufacture the plastic modules with conductive connections and they've responded positively about the idea and are willing to help out. So it may yet happen. Just depends on what I can do, given other distractions in life.

Just as a by-the-way, I spent some 1:1 time with Dr. Hennessey at MIPS, back in 1985/1986 time-frame, when working on the R2000 RISC processor (actually a small collection of chips.)